View MSP4458_2020656.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

msp 44x8g multistandard sound processor edition feb. 25, 2000 6251-516-1pd prelimina r y d a t a sheet mic r onas m i c r o n a s
msp 44x8g preliminary data sheet 2 micronas contents page section title 5 1. introduction 6 1.1. features of the msp 44x8g family 6 1.2. msp 44x8g version list 7 1.3. msp 44x8g versions and their application fields 8 2. functional description 8 2.1. architecture of the msp 44x8g family 9 2.2. msp 44x8g sound if processing 9 2.2.1. analog sound if input 9 2.2.2. demodulator: standards and features 9 2.2.3. preprocessing of demodulator signals 10 2.2.4. automatic sound select 10 2.2.5. manual mode 12 2.3. preprocessing for scart and i 2 s input signals 12 2.4. source selection and output channel matrix 12 2.4.1. mixing unit 12 2.5. audio baseband processing 12 2.5.1. automatic volume correction (avc) 13 2.5.2. main and aux outputs 13 2.5.3. quasi-peak detector 13 2.6. scart signal routing 13 2.6.1. scart dsp in and scart out select 13 2.6.2. stand-by mode 13 2.7. i 2 s bus interfaces 13 2.7.1. synchronous i 2 s-interface(s) 13 2.7.2. asynchronous i 2 s-interface 14 2.8. adr bus interface 14 2.9. digital control i/o pins and status change indication 14 2.10. preemphasis 14 2.11. clock pll oscillator and crystal specifications 15 3. control interface 15 3.1. i 2 c bus interface 15 3.1.1. device and subaddresses 16 3.1.2. description of control register 16 3.1.3. protocol description 17 3.1.4. proposals for general msp 44x8g i 2 c telegrams 17 3.1.4.1. symbols 17 3.1.4.2. write telegrams 17 3.1.4.3. read telegrams 17 3.1.4.4. examples 17 3.2. start-up sequence: power-up and i 2 c controlling 17 3.3. msp 44x8g programming interface 17 3.3.1. user registers overview 20 3.3.2. description of user registers 21 3.3.2.1. standard select register 21 3.3.2.2. standard result register
contents, continued page section title preliminary data sheet msp 44x8g micronas 3 22 3.3.2.3. write registers on i 2 c subaddress 10 hex 25 3.3.2.4. read registers on i 2 c subaddress 11 hex 26 3.3.2.5. write registers on i 2 c subaddress 12 hex 33 3.3.2.6. read registers on i 2 c subaddress 13 hex 34 3.4. programming tips 34 3.5. examples of minimum initialization codes 34 3.5.1. b/g-fm (a2 or nicam) 34 3.5.2. btsc-stereo 34 3.5.3. btsc-sap with sap at main channel 35 3.5.4. fm-stereo radio 35 3.5.5. automatic standard detection 35 3.5.6. software flow for interrupt driven status check 37 4. specifications 37 4.1. outline dimensions 39 4.2. pin connections and short descriptions 42 4.3. pin descriptions 45 4.4. pin configurations 48 4.5. pin circuits 50 4.6. electrical characteristics 50 4.6.1. absolute maximum ratings 51 4.6.2. recommended operating conditions (t a = 0 to 70 c) 51 4.6.2.1. general recommended operating conditions 51 4.6.2.2. analog input and output recommendations 52 4.6.2.3. recommendations for analog sound if input signal 53 4.6.2.4. crystal recommendations 54 4.6.3. characteristics 54 4.6.3.1. general characteristics 55 4.6.3.2. digital inputs, digital outputs 56 4.6.3.3. reset input and power-up 57 4.6.3.4. i 2 c-bus characteristics 58 4.6.3.5. i 2 s-bus characteristics 60 4.6.3.6. analog baseband inputs and outputs, agndc 62 4.6.3.7. sound if inputs 62 4.6.3.8. power supply rejection 63 4.6.3.9. analog performance 66 4.6.3.10. sound standard dependent characteristics 69 5. appendix a: overview of tv-sound standards 69 5.1. nicam 728 70 5.2. a2-systems 71 5.3. btsc-sound system 71 5.4. japanese fm stereo system (eia-j) 72 5.5. fm satellite sound 72 5.6. fm-stereo radio
msp 44x8g preliminary data sheet 4 micronas contents, continued page section title 73 6. appendix b: manual mode 73 6.1. demodulator write and read registers for manual mode 74 6.2. dsp write and read registers for manual mode 74 6.3. manual mode: description of demodulator write registers 74 6.3.1. automatic switching between nicam and analog sound 74 6.3.1.1. function in automatic sound select mode 75 6.3.1.2. function in manual mode 76 6.3.2. a2 threshold 76 6.3.3. carrier-mute threshold 77 6.3.4. dco-registers 77 6.4. manual mode: description of demodulator read registers 78 6.4.1. nicam mode control/additional data bits register 78 6.4.2. additional data bits register 78 6.4.3. cib bits register 78 6.4.4. nicam error rate register 79 6.5. manual mode: description of dsp write registers 79 6.5.1. additional channel matrix modes 79 6.5.2. fm fixed deemphasis 79 6.5.3. fm adaptive deemphasis 79 6.5.4. nicam deemphasis 79 6.5.5. identification mode for a2 stereo systems 80 6.6. manual mode: description of dsp read registers 80 6.6.1. stereo detection register for a2 stereo systems 80 6.6.2. dc level register 80 6.7. demodulator source channels in manual mode 80 6.7.1. terrestrial sound standards 80 6.7.2. sat sound standards 82 7. appendix c: application information 82 7.1. exclusions of audio baseband features 82 7.2. phase relationship of analog outputs 83 7.3. application circuit 84 8. data sheet history
preliminary data sheet msp 44x8g micronas 5 multistandard sound processor family 1. introduction the msp 44x8g family of multistandard sound pro- cessors covers the sound processing of all analog tv- standards worldwide, as well as the nicam digital sound standards. the full tv sound processing, start- ing with analog sound if signal-in, down to processed analog af-out, is performed on a single chip. fig. 1C1 shows a simplified functional block diagram of the msp 44x8g. the high-quality a/d and d/a converters offer the full audio bandwidth of 20 khz and the backend dsp pro- cessing is performed at a 48 khz sample rate. the msp 44x8g has been designed for the usage in hybrid set-top boxes and multimedia applications. its asynchronous i 2 s slave interface allows the reception of digital stereo signals with arbitrary sample rates ranging from 5 to 50 khz. synchronization is per- formed by means of an adaptive sample rate con- verter. this generation of tv sound processing ics includes versions for processing the multichannel television sound (mts) signal conforming to the standard recom- mended by the broadcast television systems commit- tee (btsc). the dbx noise reduction, or alternatively, micronas noise reduction (mnr) is performed align- ment free. other processed standards are the japanese fm-fm multiplex standard (eia-j) and the fm stereo radio standard. the msp 44x8g versions are pin and software com- patible to other msp families. standard selection requires only a single i 2 c transmission. the msp 44x8g has built-in automatic functions: the ic is able to detect the actual sound standard automat- ically (automatic standard detection). furthermore, pilot levels and identification signals can be evaluated internally with subsequent switching between mono/ stereo/bilingual; no i 2 c interaction is necessary (auto- matic sound selection). the ics are produced in submicron cmos technology and are available in the following packages: pqfp80, plqfp64, and psdip64. fig. 1C1: simplified functional block diagram of the msp 44x8g source select scart1 scart2 scart1 scart2 scart4 scart3 mono aux aux i 2 s sound processing main sound processing dac dac adc main dac dac adc i 2 s1 i 2 s2 sound if1 sound if2 channel channel i 2 s3 de- modulator dac prescale synchron. i 2 s prescale asychron. i 2 s pre- processing scart dsp input select scart output select
msp 44x8g preliminary data sheet 6 micronas 1.1. features of the msp 44x8g family 1.2. msp 44x8g version list feature 4408 4418 4428 4448 4458 standard selection with single i 2 c transmission x x x x x automatic standard detection of terrestrial tv standards x x x x x automatic sound selection (mono/stereo/bilingual), new registers modus, status x x x x x two selectable sound if (sif) inputs x x x x x automatic carrier mute function x x x x x interrupt output programmable (indicating status change) x x x x x main/aux channel with volume, balance, bass, treble, loudness x x x x x avc: automatic volume correction x x x x x two channel mixer xxxxx selectable preemphasis for aux channel x x x x x four stereo scart (line) inputs, one mono input; two stereo scart outputs x x x x x complete scart in/out switching matrix x x x x x two 48khz i 2 s inputs; one ansynchronous 5..50 khz i 2 s input, one 48 khz i 2 s output x x x x x all analog fm-stereo a2 and satellite standards; am-secam l standard x x x simultaneous demodulation of (very) high-deviation fm-mono and nicam x x adaptive deemphasis for satellite (wegener-panda, acc. to astra specification) x x x astra digital radio (adr) together with drp 3510a x x x all nicam standards xx demodulation of the btsc multiplex signal and the sap channel x x x alignment free digital dbx noise reduction for btsc stereo and sap x x alignment free digital micronas noise reduction (mnr) for btsc stereo and sap x btsc stereo and eia-j separation significantly better than spec. x x x sap and stereo detection for btsc system xxx korean fm-stereo a2 standard x x x x x alignment-free japanese standard eia-j xxx demodulation of the fm-radio multiplex signal x x x version status description msp 4408g planned fm stereo (a2) version msp 4418g planned nicam and fm stereo (a2) version msp 4428g planned ntsc version (a2 korea, btsc with micronas noise reduction (mnr), and japanese eia-j system) msp 4448g planned ntsc version (a2 korea, btsc with dbx noise reduction, and japanese eia-j system) msp 4458g available global version (all sound standards)
preliminary data sheet msp 44x8g micronas 7 1.3. msp 44x8g versions and their application fields table 1C1 provides an overview of tv sound standards that can be processed by the msp 44x8g family. in addition, the msp 44x8g is able to handle the terres- trial fm-radio standard. with the msp 44x8g, a com- plete multimedia receiver covering all tv sound stan- dards together with terrestrial and satellite radio sound can be built; even astra digital radio can be pro- cessed (with a drp 3510a coprocessor). fig. 1C2: typical msp 44x8g application table 1C1: tv stereo sound standards covered by the msp 44x8g family (details see appendix a) msp version system position of sound carrier / mhz sound modulation color system broadcast e.g. in: 4408 4418 4458 b/g 5.5/5.7421875 fm-stereo (a2) pal germany 5.5/5.85 fm-mono/nicam pal scandinavia, spain l 6.5/5.85 am-mono/nicam secam-l france i 6.0/6.552 fm-mono/nicam pal uk, hong kong d/k 6.5/5.85 fm-mono/nicam pal china, hungary 4408 6.5/6.2578125 fm-stereo (a2, d/k1) secam-east slovak. rep. 6.5/6.7421875 fm-stereo (a2, d/k2) pal currently no broadcast 6.5/5.7421875 fm-stereo (a2, d/k3) secam-east poland satellite 6.5 7.02/7.2 7.38/7.56 etc. fm-mono fm-stereo astra digital radio (adr) with drp 3510a pa l europe sat. astra 4428/48 m 4.5/4.724212 fm-stereo (a2) ntsc korea 4.5 fm-fm (eia-j) ntsc japan 4.5 btsc-stereo + sap ntsc usa fm-radio 10.7 fm-stereo radio usa, europe scart outputs 33 34 39 mh z 4.5 9 mh z main 2 2 scart2 scart1 msp 44x8g i 2 s2 i 2 s1 2 2 2 2 scart1 scart2 scart3 scart4 1 mono saw filter tuner scart inputs i 2 s3 adr composite video channel aux channel/ fm-modulator aux channel adr decoder digital signal dolby- digital/ mpeg vision demodu- lator sound if mixer
msp 44x8g preliminary data sheet 8 micronas 2. functional description 2.1. architecture of the msp 44x8g family fig. 2C1 shows a simplified block diagram of the ic. the block diagram contains all features of the msp 4458g. other members of the msp 44x8g family do not have the complete set of features, handling only a subset of the standards (see dashed block in fig. 2C1). note: * avc location is programmable (08 hex ) volume d a prescale prescale scart1 channel matrix volume daca_l daca_r source select quasi-peak detector scart2 channel matrix i 2 s channel matrix quasi-peak channel matrix main channel matrix aux channel matrix avc* volume i 2 s interface volume i 2 c read register i 2 s interface i 2 s interface sc1_in_l sc1_in_r sc2_in_l sc2_in_r sc3_in_l sc3_in_r sc4_in_l sc4_in_r mono_in prescale i2s_da_out i2s_da_in1 i2s_da_in3 d a d a synchronization / interpolation (sync. 48 khz) (async. 5-50 khz) a d dacm_l dacm_r d a preem- phasis automatic soundselect deemphasis: 50/75 m s dbx/mnr panda1 deemphasis: j17 a d prescale agc ana_in1+ ana_in2+ standard and sound detection i 2 c read register demodulator (incl. carrier mute) decoded standards: nicam a2 am btsc eia-j sat fm-radio fm/am stereo or a stereo or a stereo or b nicam adr-bus interface i 2 s1 i 2 s3 scart scale mix2 scale mix1 s scart dsp input select sc1_out_l sc1_out_r sc2_out_l sc2_out_r scart output select scart1_l/r scart2_l/r 0 1 3 4 5 7 15 2 i 2 s interface prescale i2s_da_in2 i 2 s2 6 (sync. 48 khz) mix1 channel matrix mix2 channel matrix (sync. 48 khz) i2s_cl i2s_ws i2s_cl3 i2s_ws3 (16 hex ) (12 hex ) (11 hex ) (0d hex ) (0e hex ) (10 hex ) (09 hex ) (0b hex ) (0c hex ) (38 hex ) (39 hex ) (0a hex ) (41 hex ) (3a hex ) (3b hex ) (06 hex ) (07 hex ) (40 hex ) (00 hex ) (29 hex ) (34 hex ) beeper s s (14 hex ) avc* prescale fm/am fig. 2 C1: signal flow block diagram of the msp 44x8g (input and output names correspond to pin names). (13 hex ) (13 hex ) (29 hex )
preliminary data sheet msp 44x8g micronas 9 2.2. msp 44x8g sound if processing 2.2.1. analog sound if input the input pins ana_in1+, ana_in2+, and ana_in - offer the possibility to connect two different s ound if ( sif ) sources to the msp 44x8g. the preselected sound if signal is fed into an a/d-converter. an analog a utomatic g ain c ircuit ( agc ) allows a wide range of input levels. the highpass filters, formed by the cou- pling capacitors at pins ana_in1+ and ana_in2+ (see section 7.3. application circuit on page 83), are sufficient in most cases to suppress video compo- nents. some combinations of saw filters and sound if mixer ics, however, show large picture components on their outputs. in this case, further filtering is recom- mended. 2.2.2. demodulator: standards and features the msp 44x8g is able to demodulate all tv-sound standards worldwide including the digital nicam sys- tem. depending on the msp 44x8g version, the fol- lowing demodulation modes can be performed: a2 systems: detection and demodulation of two sep- arate fm carriers (fm1 and fm2), demodulation and evaluation of the identification signal of carrier fm2. nicam systems: (only possible in the msp 4418g and msp 4458g). demodulation and decoding of the nicam carrier, detection and demodulation of the ana- log fm or am carrier. for d/k-nicam, the fm carrier may have a maximum deviation of 384 khz. very high deviation fm-mono: detection and robust demodulation of one fm carrier with a maximum devi- ation of 540 khz. btsc-stereo: detection and fm demodulation of the aural carrier resulting in the mts/mpx signal. detec- tion and evaluation of the pilot carrier, am demodula- tion of the (l - r)-carrier and detection of the sap sub- carrier. processing of dbx noise reduction or m icronas n oise r eduction ( mnr ). btsc-mono + sap: detection and fm demodulation of the aural carrier resulting in the mts/mpx signal. detection and evaluation of the pilot carrier, detection and fm demodulation of the sap subcarrier. process- ing of dbx noise reduction or micronas noise reduc- tion (mnr). japan stereo: detection and fm demodulation of the aural carrier resulting in the mpx signal. demodulation and evaluation of the identification signal and fm demodulation of the (l - r)-carrier. fm-satellite sound: demodulation of one or two fm carriers. processing of high-deviation mono or narrow bandwidth mono, stereo, or bilingual satellite sound according to the astra specification. fm-stereo-radio: detection and fm demodulation of the aural carrier resulting in the mpx signal. detection and evaluation of the pilot carrier and am demodula- tion of the (l - r)-carrier. the demodulator blocks of all msp 44x8g versions have identical user interfaces. even completely differ- ent systems like the btsc and nicam systems are controlled the same way. standards are selected by means of msp standard codes. automatic processes handle standard detection and identification without controller interaction. the key features of the msp 44x8g demodulator blocks are described below. standard selection: the controlling of the demodula- tor is minimized: all parameters, such as tuning fre- quencies or filter bandwidth, are adjusted automati- cally by transmitting one single value to the standard select register. for all standards, spe- cific msp standard codes are defined. automatic standard detection: if the tv sound stan- dard is unknown, the msp 44x8g can automatically detect the actual standard, switch to that standard, and respond the actual msp standard code. automatic carrier mute: to prevent noise effects or fm identification problems in the absence of an fm carrier, the msp 44x8g offers a carrier mute feature, which is activated automatically if the standard is selected by means of the standard select regis- ter. if no fm carrier is available at one of the two msp demodulator channels, the corresponding demodula- tor output is muted. 2.2.3. preprocessing of demodulator signals all demodulated signals must be processed by a deemphasis filter and adjusted in level (analog signals must also be dematrixed). the correct deemphasis fil- ters are already selected by setting the standard in the standard select register. the level adjustment has to be done by means of the fm/am and nicam prescale registers. the necessary dematrix function depends on the selected sound standard and the actual broadcasted sound mode (mono, stereo, or bilingual). it can be manually set by the fm matrix mode register or automatically set by the automatic sound selection.
msp 44x8g preliminary data sheet 10 micronas 2.2.4. automatic sound select in the automatic sound select mode, the dematrix function is automatically selected based on the identifi- cation information in the status register. no i 2 c inter- action is necessary when the broadcasted sound mode changes (e.g. from mono to stereo). the demodulator supports the identification check by switching between mono compatible standards (stan- dards that have the same fm mono carrier) automati- cally and non-audible. if b/g-fm or b/g-nicam is selected, the msp will switch between these stan- dards. the same action is performed for the standards: d/k1-fm, d/k2-fm, and d/k-nicam. switching is only done in the absence of any stereo or bilingual identifi- cation. if identification is found, the msp keeps the detected standard. in case of high bit-error rates, the msp 44x8g auto- matically falls back from digital nicam sound to ana- log fm or am mono. table 2C1 on page 11 summarizes all actions that take place when automatic sound select is switched on. to provide more flexibility, the automatic sound select block prepares four different source channels of demodulated sound (fig. 2C2). by choosing one of the four demodulator channels, the preferred sound mode can be selected by means of the source select regis- ters, independent for all msp-outputs. the following source channels of demodulated sound are defined: C fm/am channel: analog mono sound, stereo if available. in case of nicam, analog mono only (fm or am mono). C stereo or a/b channel: analog or digital mono sound, stereo if available. in case of bilingual broad- cast, it contains both languages a (left) and b (right). C stereo or a channel: analog or digital mono sound, stereo if available. in case of bilingual broad- cast, it contains language a (on left and right). C stereo or b channel: analog or digital mono sound, stereo if available. in case of bilingual broad- cast, it contains language b (on left and right). fig. 2C2 and table 2C2 show the source channel assignment of the demodulated signals in case of automatic sound select mode for all sound standards (see section 6.). note: the analog primary input channel contains the signal of the mono fm/am carrier or the l+r signal of the mpx carrier. the secondary input channel con- tains the signal of the second fm carrier, the l - r sig- nal of the mpx carrier, or the sap signal. fig. 2C2: source channel assignment of demodulated signals in automatic sound select mode 2.2.5. manual mode fig. 2C3 shows the source channel assignment of demodulated signals in case of manual mode. if man- ual mode is required, more information can be found in section 6.7. demodulator source channels in manual mode on page 80. fig. 2C3: source channel assignment of demodulated signals in manual mode prescale automatic sound select source select nicam a nicam fm/am prescale nicam fm/am stereo or a/b stereo or a stereo or b 0 1 3 4 primary channel secondary channel ls ch. matrix sc2 ch. matrix output-ch. matrices must be set once to stereo prescale source select primary channel secondary channel nicam a nicam fm/am prescale nicam fm/am (stereo or a/b) 0 1 fm-matrix nicam ls ch. matrix sc2 ch. matrix output-ch. matrices must be set according the standard
preliminary data sheet msp 44x8g micronas 11 table 2C1: performed actions of the automatic sound selection selected tv sound standard performed actions b/g-fm, d/k-fm, m-korea, and m-japan evaluation of the identification signal and automatic switching to mono, stereo, or bilingual. preparing four demodulator source channels according to table 2C2. identification is acquired after 500 ms. b/g-nicam, l-nicam, i-nicam, and d/k-nicam evaluation of nicam-c-bits and automatic switching to mono, stereo, or bilingual. preparing four demodulator source channels according to table 2C2. nicam detection is acquired within 150 ms. in case of bad or no nicam reception, the msp switches automatically to fm/am mono and switches back to nicam if possible. a hysteresis prevents periodical switching. b/g-fm, b/g-nicam or d/k1-fm, d/k2-fm, d/k-nicam automatic searching for stereo/bilingual-identification in case of mono transmission. automatic and non- audible changes between dual-fm and fm-nicam standards while listening to the basic fm-mono sound carrier. example: if starting with b/g-fm-stereo, there will be a periodical alternation to b/g-nicam in the absence of fm-stereo/bilingual or nicam-identification. once an identification is detected, the msp keeps the corresponding standard. btsc-stereo, fm radio evaluation of the pilot signal and automatic switching to mono or stereo. preparing four demodulator source channels according to table 2C2. detection of the sap carrier. pilot detection is acquired after 200 ms. btsc-sap in the absence of sap, the msp switches to btsc-stereo if available. if sap is detected, the msp switches automatically to sap (see table 2C2). table 2C2: sound modes for the demodulator source channels with automatic sound select source channels in automatic sound select mode broadcasted sound standard selected msp standard code 3) broadcasted sound mode fm/am (source select: 0) stereo or a/b (source select: 1) stereo or a (source select: 3) stereo or b (source select: 4) m-korea b/g-fm d/k-fm m-japan 02 03, 08 1) 04, 05, 0b 1) 30 mono mono mono mono mono stereo stereo stereo stereo stereo bilingual: languages a and b left = a right = b left = a right = b ab b/g-nicam l-nicam i-nicam d/k-nicam d/k-nicam (with high deviation fm) 08, 03 2) 09 0a 0b, 04 2) , 05 2) 0c nicam not available or error rate too high analog mono analog mono analog mono analog mono mono analog mono nicam mono nicam mono nicam mono stereo analog mono nicam stereo nicam stereo nicam stereo bilingual: languages a and b analog mono left = nicam a right = nicam b nicam a nicam b btsc 20, 21 mono mono mono mono mono stereo stereo stereo stereo stereo 20 mono+sap mono mono mono mono stereo+sap stereo stereo stereo stereo 21 mono+sap left = mono right = sap left = mono right = sap mono sap stereo+sap left = mono right = sap left = mono right = sap mono sap fm radio 40 mono mono mono mono mono stereo stereo stereo stereo stereo 1) the automatic sound select process will automatically switch to the mono compatible analog standard. 2) the automatic sound select process will automatically switch to the mono compatible digital standard. 3) the msp standard codes are defined in table 3C7 on page 20.
msp 44x8g preliminary data sheet 12 micronas 2.3. preprocessing for scart and i 2 s input signals the scart and i 2 s inputs need only be adjusted in level by means of the scart and i 2 s prescale regis- ters. 2.4. source selection and output channel matrix the source selector makes it possible to distribute all source signals (one of the demodulator source chan- nels, scart, or i 2 s input) to the desired output chan- nels (main, aux, etc.). all input and output signals can be processed simultaneously. each source channel is identified by a unique source address. for each output channel, the output channel matrix can be set to sound a, sound b, stereo, or mono. if automatic sound select is on, the output channel matrix can stay fixed to stereo (transparent) for demod- ulated signals. 2.4.1. mixing unit any source can be selected as the input for the two channels of the mixing unit. the mixer channel matri- ces and the scaling factors can be programmed sepa- rately for each channel. after adding up both channels, the signal is fed back and is available as source 15 (mix output) of the source selector. 2.5. audio baseband processing 2.5.1. automatic volume correction (avc) different sound sources (e.g. terrestrial channels, sat channels, or scart) fairly often do not have the same volume level. advertisements during movies usually have a higher volume level than the movie itself. this results in annoying volume changes. the avc solves this problem by equalizing the volume level. in the standard configuration the avc block is located in the main channel. alternatively, the avc function can be moved to the mixer path. to prevent clipping, the avcs gain decreases quickly in dynamic boost conditions. to suppress oscillation effects, the gain increases rather slowly for low-level inputs. the decay time is programmable by the avc register (see page 29). for input signals ranging from - 24 dbr to 0 dbr, the avc maintains a fixed output level of - 18 dbr. fig. 2C4 shows the avc output level versus its input level. for prescale and volume registers set to 0 db, a level of 0 dbr corresponds to full scale input/output. this is C scart input/output 0 dbr = 2.0 v rms C main and aux output 0 dbr = 1.4 v rms fig. 2C4: simplified avc characteristics - 30 - 24 - 18 - 12 - 6 + 6 input level - 18 - 24 - 12 output level 0 [dbr] [dbr]
preliminary data sheet msp 44x8g micronas 13 2.5.2. main and aux outputs the main and aux output channels are adjustable in volume. a square wave beeper with adjustable fre- quency and volume can be added to them. 2.5.3. quasi-peak detector the quasi-peak readout register can be used to read out the quasi-peak level of any input source. the fea- ture is based on following filter time constants: C attack time: 1.3 ms C decay time: 37 ms 2.6. scart signal routing 2.6.1. scart dsp in and scart out select the scart dsp input select and scart output select blocks include full matrix switching facilities. to design a tv set with four pairs of scart-inputs and two pairs of scart-outputs, no external switching hardware is required. the switches are controlled by the acb user register (see page 31). 2.6.2. stand-by mode if the msp 44x8g is switched off by first pulling standbyq low and then (after >1 m s delay) switching off the 5-v, but keeping the 8-v power supply ( stand- by-mode ), the scart switches maintain their posi- tion and function. this allows the copying from selected scart-inputs to scart-outputs in the tv sets stand-by mode. in case of power on or starting from stand-by (see details on the power-up sequence in fig. 4C20 on page 56), all internal registers except the acb register (page 31) are reset to the default configuration (see table 3C5 on page 18). the reset position of the acb register becomes active after the first i 2 c transmission into the baseband processing part (subaddress 12 hex ). by transmitting the acb register first, the reset state can be redefined. 2.7. i 2 s bus interfaces the msp 44x8g has two kinds of interfaces: synchro- nous master/slave input/output interfaces running on 48 khz and an asynchronous slave interface. the interfaces accept a variety of formats with different sample width, bit-orientation, and wordstrobe timing. all i 2 s options are set by means of the modus or i 2 s_config register. 2.7.1. synchronous i 2 s-interface(s) the synchronous i 2 s bus interface consists of the pins: C i2s_da_in1, i2s_da_in2/3 (i2s_da_in2 in pqfp80 package): i 2 s serial data input, 16, 18...32 bits per sample. C i2s_da_out: i 2 s serial data output, 16, 18...32 bits per sample. C i2s_cl: i 2 s serial clock. C i2s_ws: i 2 s word strobe signal defines the left and right sample. if the msp 44x8g serves as the master on the i 2 s interface, the clock and word strobe lines are driven by the msp. in this mode, only 16, 32 bits per sample can be selected. in slave mode, these lines are input to the msp 44x8g and the msp clock is synchronized to 384 times the i2s_ws rate (48 khz). nicam operation is not possible in slave mode. an i 2 s timing diagram is shown in fig. 4C22 on page 59. 2.7.2. asynchronous i 2 s-interface the asynchronous i 2 s slave interface allows the reception of digital stereo signals with arbitrary sample rates from 5 to 50 khz. the synchronization is per- formed by means of an adaptive sample rate con- verter. no oversampling clock is required. the following pins are used for the asynchronous i 2 s bus interface: C i2s_ws3 (serves only as input) C i2s_cl3 (serves only as input) C i2s_da_in2/3 (i2s_da_in3 in pqfp80 package). the interface accepts i 2 s-input streams with msb first and with sample widths of 16,18...32 bits. with left/ right alignment and wordstrobe timing polarity, there are additional parameters available for the adaption to a variety of formats in the i 2 s-config register (see page 24).
msp 44x8g preliminary data sheet 14 micronas 2.8. adr bus interface for the astra digital radio system (adr), the msp 4408g, msp 4418g, and msp 4458g performs preprocessing such as carrier selection and filtering. via the 3-line adr-bus, the resulting signals are trans- ferred to the drp 3510a coprocessor, where the source decoding is performed. to be prepared for an upgrade to adr with an additional drp board, the fol- lowing lines of msp 44x8g should be provided on a feature connector: C aud_cl_out C i2s_da_in1, 2, or 3 C i2s_da_out, i2s_ws, i2s_cl C adr_cl, adr_ws, adr_da for more details, please refer to the drp 3510a data sheet. 2.9. digital control i/o pins and status change indication the static level of the digital input/output pins d_ctr_i/o_0/1 is switchable between high and low via the i 2 c-bus by means of the acb register (see page 31). this enables the controlling of external hardware switches or other devices via i 2 c-bus. the digital input/output pins can be set to high imped- ance by means of the modus register (see page 23). in this mode, the pins can be used as input. the cur- rent state can be read out of the status register (see page 25). optionally, the pin d_ctr_i/o_1 can be used as an interrupt request signal to the controller, indicating any changes in the read register status. this makes poll- ing unnecessary, i 2 c bus interactions are reduced to a minimum (see status register on page 25 and modus register on page 23). 2.10. preemphasis when using the aux output for feeding an external modulator, a preemphasis can be applied to the right channel. the signal is scaled down by - 3 db. an overmodula- tion protection is included in the algorithm which limits the output signal to 0 dbfs. due to the nature of a pre- emphasis, its gain at high frequencies exceeds 3 db. thus, even with 0 db input signals and prescaler / vol- ume set to 0 db, clipping can occur. there are three modes present: preemphasis off, 50 m s, and 75 m s. (see table 3C11on page 29) for the register settings. 2.11. clock pll oscillator and crystal specifications the msp 44x8g derives all internal system clocks from the 18.432 mhz oscillator. in nicam or in i 2 s- slave mode of the synchronous interface, the clock is phase-locked to the corresponding source. therefore, it is not possible to use nicam and i 2 s-slave mode of the synchronous interface at the same time. for proper performance, the msp clock oscillator requires a 18.432-mhz crystal. note that for the phase-locked modes (nicam, i 2 s-slave), crystals with tighter tolerance are required. please note also, that the asynchronous i 2 s3 slave interface uses a different locking mechanism and does not require tighter crystal tolerances. remark on using the crystal: external capacitors at each crystal pin to ground are required. they are necessary for tuning the open-loop frequency of the internal pll and for stabilizing the fre- quency in closed-loop operation. the higher the capacitors, the lower the resulting clock frequency. the nominal free running frequency should match 18.432 mhz as closely as possible. clock measurements should be done at pin aud_cl_out. this pin must be activated for this pur- pose (see modus register on page 23).
preliminary data sheet msp 44x8g micronas 15 3. control interface 3.1. i 2 c bus interface 3.1.1. device and subaddresses the msp 44x8g is controlled via the i 2 c bus slave interface. the ic is selected by transmitting one of the msp 44x8g device addresses. in order to allow up to three msp ics to be connected to a single bus, an address select pin (adr_sel) has been implemented. with adr_sel pulled to high, low, or left open, the msp 44x8g responds to different device addresses. a device address pair is defined as a write address and a read address (see table 3C1). writing is done by sending the device write address, followed by the subaddress byte, two address bytes, and two data bytes. reading is done by sending the write device address, followed by the subaddress byte and two address bytes. without sending a stop condi- tion, reading of the addressed data is completed by sending the device read address and reading two bytes of data. refer to section 3.1.2. for the i 2 c bus protocol and to section 3.4. programming tips on page 34 for proposals of msp 44x8g i 2 c telegrams. see table 3C2 for a list of available subaddresses. besides the possibility of hardware reset, the msp can also be reset by means of the reset bit in the con- trol register by the controller via i 2 c bus. due to the internal architecture of the msp 44x8g, the ic cannot react immediately to an i 2 c request. the typical response time is about 0.3 ms. if the msp can- not accept another complete byte of data until it has performed some other function (for example, servicing an internal interrupt), it will hold the clock line i2c_cl low to force the transmitter into a wait state. the posi- tions within a transmission where this may happen are indicated by wait in section 3.1.3. the maximum wait period of the msp during normal operation mode is less than 1 ms. internal hardware error handling: in case of any internal hardware error (e.g. interruption of the power supply of the msp), the msps wait period is extended to 1.8 ms. after this time period elapses, the msp releases data and clock lines. indication and solving of the error status: to indicate the error status, the remaining acknowl- edge bits of the actual i 2 c-protocol will be left high. additionally, bit[14] of control is set to one. the msp can then be reset via the i 2 c bus by transmitting the reset condition to control. indication of reset: any reset, even caused by an unstable reset line etc., is indicated in bit[15] of control. a general timing diagram of the i 2 c bus is shown in fig. 4C21 on page 57. table 3C1: i 2 c bus device addresses adr_sel low high left open mode write read write read write read msp device address 80 hex 81 hex 84 hex 85 hex 88 hex 89 hex table 3C2: i 2 c bus subaddresses name binary value hex value mode function control 0000 0000 00 read/write write: software reset of msp (see table 3C3) read: hardware error status of msp test 0000 0001 01 write only for internal use wr_dem 0001 0000 10 write write address demodulator rd_dem 0001 0001 11 write read address demodulator wr_dsp 0001 0010 12 write write address dsp rd_dsp 0001 0011 13 write read address dsp
msp 44x8g preliminary data sheet 16 micronas 3.1.2. description of control register 3.1.3. protocol description write to dsp or demodulator read from dsp or demodulator write to control or test registers note: s = i 2 c-bus start condition from master p = i 2 c-bus stop condition from master ack = acknowledge-bit: low on i2c_da from slave (= msp, light gray) or master (= controller, dark gray) nak = not acknowledge-bit: high on i2c_da from master (dark gray) to indicate end of read or from msp indicating internal error state wait = i 2 c-clock line is held low, while the msp is processing the i 2 c command. fig. 3C1: i 2 c bus protocol (msb first; data must be stable while clock is high) table 3C3: control as a write register name subaddress bit[15] (msb) bits[14:0] control 00 hex 1 : reset 0 : normal 0 table 3C4: control as a read register name subaddress bit[15] (msb) bit[14] bits[13:0] control 00 hex reset status after last reading of control: 0 : no reset occured 1 : reset occured internal hardware status: 0 : no error occured 1 : internal error occured not of interest reading of control will reset the bits[15,14] of control. after power-on, bit[15] of control will be set; it must be read once to be reset. swrite device address wait ack sub-addr ack addr-byte high ack addr-byte low ack data-byte- high ack data-byte low ack p swrite device address wait ack sub-addr ack addr-byte high ack addr-byte low ack s read device address wait ack data-byte- high ack data-byte low nak p swrite device address wait ack sub-addr ack data-byte high ack data-byte low ack p 1 0 s p i2c_da i2c_cl
preliminary data sheet msp 44x8g micronas 17 3.1.4. proposals for general msp 44x8g i 2 c telegrams 3.1.4.1. symbols daw write device address (80 hex , 84 hex or 88 hex ) dar read device address (81 hex , 85 hex or 89 hex ) < start condition > stop condition aa address byte dd data byte 3.1.4.2. write telegrams write to control register write data into demodulator write data into dsp 3.1.4.3. read telegrams read data from demodulator read data from dsp 3.1.4.4. examples <80 00 80 00> reset msp statically <80 00 00 00> clear reset <80 10 00 20 00 03> set demodulator to stand. 03 hex <80 11 02 00 <81 dd dd> read status <80 12 00 08 01 20> set main channel source to nicam and matrix to stereo more examples of typical application protocols are listed in section 3.4. programming tips on page 34. 3.2. start-up sequence: power-up and i 2 c controlling after power on or reset (see fig. 4C20 on page 56), the ic is in an inactive state. all registers are in the reset position (seetable 3C5 and table 3C6), the analog outputs are muted. the controller has to initial- ize all registers for which a non-default setting is nec- essary. 3.3. msp 44x8g programming interface 3.3.1. user registers overview the msp 44x8g is controlled by means of user regis- ters. the complete list of all user registers is given in the following tables. the registers are partitioned into the demodulator section (subaddress 10 hex for writing, 11 hex for reading) and the baseband processing sec- tions (subaddress 12 hex for writing, 13 hex for reading). write and read registers are 16-bit wide, whereby the msb is denoted bit[15]. transmissions via i 2 c bus have to take place in 16-bit words (two byte transfers, with the most significant byte transferred first). all write registers, except the demodulator write registers, are readable. unused parts of the 16-bit write registers must be zero. addresses not given in this table must not be written. an overview of all msp 44x8g write registers is shown in table 3C5; all read registers are given in table 3C6. additional read and write registers, together with a detailed description of the manual mode, can be found in the appendix b: manual mode on page 73.
msp 44x8g preliminary data sheet 18 micronas table 3C5: list of msp 44x8g write registers write register address (hex) bits description and adjustable range reset see page i 2 c subaddress = 10 hex ; registers are not readable standard select 00 20 [15:0] initial programming of complete demodulator 00 00 21 modus 00 30 [15:0] demodulator, automatic and i 2 s options 00 00 22 i 2 c subaddress = 12 hex ; registers are all readable by using i 2 c subaddress = 13 hex volume main channel 00 00 [15:8] [ + 12 db ... - 114 db, mute] mute 29 [7:5] [4:0] 1/8 db steps must be set to 0 000 bin 00000 bin volume aux channel 00 06 [15:8] [ + 12 db ... - 114 db, mute] mute 29 [7:5] [4:0] 1/8 db steps must be set to 0 000 bin 00000 bin volume scart1 output channel 00 07 [15:8] [ + 12 db ... - 114 db, mute] mute 30 main source select 00 08 [15:8] [fm/am, nicam, scart, i 2 s1..3, mix output] fm/am 28 main channel matrix [7:0] [sounda, soundb, stereo, mono] sounda 28 aux source select 00 09 [15:8] [fm/am, nicam, scart, i 2 s1..3, mix output] fm/am 28 aux channel matrix [7:0] [sounda, soundb, stereo, mono] sounda 28 scart1 source select 00 0a [15:8] [fm/am, nicam, scart, i 2 s1..3, mix output] fm/am 28 scart1 channel matrix [7:0] [sounda, soundb, stereo, mono] sounda 28 i 2 s source select 00 0b [15:8] [fm/am, nicam, scart, i 2 s1..3, mix output] fm/am 28 i 2 s channel matrix [7:0] [sounda, soundb, stereo, mono] sounda 28 quasi-peak detector source select 00 0c [15:8] [fm/am, nicam, scart, i 2 s1..3, mix output] fm/am 28 quasi-peak detector matrix [7:0] [sounda, soundb, stereo, mono] sounda 28 prescale scart input 00 0d [15:8] [00 hex ... 7f hex ]00 hex 27 prescale fm/am 00 0e [15:8] [00 hex ... 7f hex ]00 hex 26 fm matrix [7:0] [no_mat, gstereo, kstereo] no_mat 27 prescale nicam 00 10 [15:8] [00 hex ... 7f hex ]00 hex 27 prescale i 2 s3 00 11 [15:8] [00 hex ... 7f hex ]10 hex 27 prescale i 2 s2 00 12 [15:8] [00 hex ... 7f hex ]10 hex 27 scart switches and d_ctr_i/o 00 13 [15:0] bits [15:0] 00 hex 31 beeper 00 14 [15:0] [00 hex ... 7f hex ]/[00 hex ... 7f hex ] 00/00 hex 32 prescale i 2 s1 00 16 [15:8] [00 hex ... 7f hex ]10 hex 27 avc: automatic volume correction 00 29 [15:8] [off, on, decay time] off 29 aux preemphasis on right channel 00 34 [15:8] [off, 50s, 75s] off 29 mix1 source select 00 38 [15:8] [fm/am, nicam, scart, i 2 s1..3, mix output] fm/am 28 mix1 channel matrix [7:0] [sounda, soundb, stereo, mono] sounda 28 mix2 source select 00 39 [15:8] [fm/am, nicam, scart, i 2 s1..3, mix output] fm/am 28 mix2 channel matrix [7:0] [sounda, soundb, stereo, mono] sounda 28 scale mix1 00 3a [15:8] [00 hex ... 7f hex ]00 hex 32 scale mix2 00 3b [15:8] [00 hex ... 7f hex ]00 hex 32
preliminary data sheet msp 44x8g micronas 19 volume scart2 output channel 00 40 [15:8] [ + 12 db ... - 114 db, mute] 00 hex 30 scart2 source select 00 41 [15:8] [fm/am, nicam, scart, i 2 s1..3, mix output] fm 28 scart2 channel matrix [7:0] [sounda, soundb, stereo, mono] sounda 28 table 3C6: list of msp 44x8g read registers read register address (hex) bits description and adjustable range see page i 2 c subaddress = 11 hex ; registers are not writable standard result 00 7e [15:0] result of automatic standard detection (see table 3C8) 25 status 02 00 [15:0] monitoring of settings e.g. stereo, mono, mute, d_ctr_i/o etc. . 25 i 2 c subaddress = 13 hex ; registers are not writable quasi peak readout left 00 19 [15:0] [00 hex ... 7fff hex ]16 bit twos complement 33 quasi peak readout right 00 1a [15:0] [00 hex ... 7fff hex ]16 bit twos complement 33 msp hardware version code 00 1e [15:8] [00 hex ... ff hex ]33 msp major revision code [7:0] [00 hex ... ff hex ]33 msp product code 00 1f [15:8] [00 hex ... ff hex ]33 msp rom version code [7:0] [00 hex ... ff hex ]33 table 3C5: list of msp 44x8g write registers, continued write register address (hex) bits description and adjustable range reset see page
msp 44x8g preliminary data sheet 20 micronas 3.3.2. description of user registers table 3C7: standard codes for standard select register msp standard code (data in hex) tv sound standard sound carrier frequencies in mhz msp 44x8g version automatic standard detection 00 01 start automatic standard detection all standard selection 00 02 m-dual fm-stereo 4.5/4.724212 4408, 4418, 4448, 4458 00 03 b/g-dual fm-stereo 1) 5.5/5.7421875 4408, 4418, 4458 00 04 d/k1-dual fm-stereo 2) 6.5/6.2578125 00 05 d/k2-dual fm-stereo 2) 6.5/6.7421875 00 06 d/k-fm-mono with hdev3 3) , not detectable by automatic standard detection, for china hdev3 3) sat-mono (i.e. eutelsat, see table 6C12) 6.5 00 07 d/k3-dual fm-stereo 6.5/5.7421875 4408, 4418, 4458 00 08 b/g-nicam-fm 1) 5.5/5.85 4418, 4458 00 09 l-nicam-am 6.5/5.85 00 0a i-nicam-fm 6.0/6.552 00 0b d/k-nicam-fm 2) 6.5/5.85 00 0c d/k-nicam-fm with hdev2 4) , not detectable by automatic standard detection, for china 6.5/5.85 00 0d d/k-nicam-fm with hdev3 3) , not detectable by automatic standard detection, for china 6.5/5.85 4418, 4458 00 20 btsc-stereo 4.5 4438, 4448, 4458 00 21 btsc-mono + sap 00 30 eia-j japan stereo 4.5 4448, 4458 00 40 fm-stereo radio 10.7 4438, 4448, 4458 00 50 sat-mono (see table 6C12) 6.5 4408, 4418, 4458 00 51 sat-stereo (see table 6C12) 7.02/7.20 4408, 4418, 4458 00 60 sat adr (astra digital radio) 6.12 4408, 4418, 4458 1) in case of automatic sound select, the b/g-codes 3 hex and 8 hex are equivalent. 2) in case of automatic sound select, the d/k-codes 4 hex , 5 hex , 7 hex and b hex are equivalent. 3) hdev3: max. fm deviation must not exceed 540 khz 4) hdev2: max. fm deviation must not exceed 360 khz
preliminary data sheet msp 44x8g micronas 21 3.3.2.1. standard select register the tv sound standard of the msp 44x8g demodula- tor is determined by the standard select register. there are two ways to use the standard select register: C setting up the demodulator for a tv sound standard by sending the corresponding standard code with a single i 2 c-bus transmission. C starting the automatic standard detection for ter- restrial tv standards. this is the most comfortable way to set up the demodulator. within 0.5 s, the detection and set-up of the actual tv sound stan- dard is performed. the detected standard can be read out of the standard result register by the control processor. this feature is recommended for the primary set-up of a tv set. outputs should be muted during automatic standard detection. the standard codes are listed in table 3C7. selecting a tv sound standard via the standard select register initializes the demodulator. this includes: agc, tuning frequency, band-pass filters, demodulation mode (fm, am, or nicam), carrier mute, deemphasis, and identification mode. if a present sound standard is impossible for a specific msp version, it switches to the analog mono sound of this standard. in that case, stereo or bilingual process- ing will not be possible. for a complete setup of the tv sound processing from analog if input to the source selection, the following transmissions are necessary: modus register, stan- dard select register, prescale values, fm matrix. note: the fm matrix is set automatically if automatic sound select is active (modus[0]=1). in this case, the fm matrix will be initialized with sound a mono. dur- ing operation, the fm matrix will be automatically selected according to the actual identification informa- tion. 3.3.2.2. standard result register if automatic standard detection is selected in the standard select register, status and result of the automatic standard detection process can be read out of the standard result register. the possible results are based on the mentioned standard code and are listed in table 3C8. in cases where no sound standard has been detected (no standard present, too much noise, strong interfer- ers, etc.) the standard result register contains 00 00 hex . in that case, the controller has to start further actions (for example, set the standard according to a preference list or by manual input). as long as the standard result register contains a value greater than 07 ff hex , the automatic standard detection is still active. during this period, the modus and standard select register must not be written. the status register will be updated when the auto- matic standard detection has finished. if a present sound standard is impossible for a specific msp version, it detects and switches to the analog mono sound of this standard. example: the msps 4438g and 4448g will detect a b/g-nicam signal as standard 3 and will switch to the analog fm- mono sound. table 3C8: results of the automatic standard detection broadcasted sound standard standard result register read 007e hex automatic standard detection could not find a sound standard 0000 hex b/g-fm 0003 hex b/g-nicam 0008 hex i 000a hex fm-radio 0040 hex m-fm eia-j btsc 0002 hex (if modus[14,13]=00) 0020 hex (if modus[14,13]=01) 0030 hex (if modus[14,13]=10) l-am d/k1 d/k2 0009 hex (if modus[12]=0) 0004 hex (if modus[12]=1) l-nicam d/k-nicam 0009 hex (if modus[12]=0) 000b hex (if modus[12]=1) automatic standard detection still active >07ff hex
msp 44x8g preliminary data sheet 22 micronas 3.3.2.3. write registers on i 2 c subaddress 10 hex table 3C9: write registers on i 2 c subaddress 10 hex register address function name standard selection 00 20 hex standard selection register defines tv sound or fm-radio standard bit[15:0] 00 01 hex start automatic standard detection 00 02 hex standard codes (see table 3C7)) ... 00 60 hex standard_sel
preliminary data sheet msp 44x8g micronas 23 modus 00 30 hex modus register general msp 44x8g options bit[15] 0 undefined, must be 0 bit[14:13] detected 4.5 mhz carrier is interpreted as: 1) 0 standard m (korea) 1 standard m (btsc) 2 standard m (japan) 3 carrier at 4.5 mhz is ignored (chroma carrier) preference in automatic standard detection: bit[12] detected 6.5 mhz carrier is interpreted as: 1) 0 standard l (secam) 1 standard d/k1, d/k2, or d/k nicam bit[11:9] 0 undefined, must be 0 bit[8] 0/1 ana_in_1 + /ana_in_2 + ; select analog sound if input pin bit[7] 0/1 active/tristate state of audio clock output pin aud_cl_out bit[6] word strobe alignment (synchronous i 2 s) 0 ws changes at data word boundary 1 ws changes one clock cycle in advance bit[5] 0/1 master/slave mode of i 2 s interface (must be set to 0 (= master) in case of nicam mode) bit[4] 0/1 active/tristate state of i 2 s output pins bit[3] state of digital output pins d_ctr_i/o_0 and _1 0 active: d_ctr_i/o_0 and _1 are output pins (can be set by means of the acb register. see also: modus[1]) 1 tristate: d_ctr_i/o_0 and _1 are input pins (level can be read out of status[4,3]) bit[2] 0 undefined, must be 0 bit[1] 0/1 disable/enable status change indication by means of the digital i/o pin d_ctr_i/o_1 necessary condition: modus[3] = 0 (active) bit[0] 0/1 off/on: automatic sound select modus 1) valid at the next start of automatic standard detection. table 3C9: write registers on i 2 c subaddress 10 hex , continued register address function name
msp 44x8g preliminary data sheet 24 micronas 0040 hex i 2 s configuration register (not mentioned bit combinations must not be used) bit[15:12] 0 undefined, must be set to 0 bit[11] i 2 s data alignment (i 2 s_3) 0 left aligned 1 right aligned bit[10] word strobe polarity (i 2 s_3) 1 0 = right, 1 = left 0 1 = right, 0 = left bit[9] word strobe alignment (asynchronous i 2 s_3) 0 ws changes at data word boundary 1 ws changes one clock cycle in advance bit[8:2] 0 undefined, must be set to 0 bit[1:0] i2s_cl frequency and i 2 s_da_out sample length 00 2 * 16bit (1.536mhz clk) 01 2 * 32bit (3.072mhz clk) 1x undefined, must not be used i2s_config table 3C9: write registers on i 2 c subaddress 10 hex , continued register address function name
preliminary data sheet msp 44x8g micronas 25 3.3.2.4. read registers on i 2 c subaddress 11 hex table 3C10: read registers on i 2 c subaddress 11 hex register address function name standard result 00 7e hex standard result register readback of the detected tv sound or fm-radio standard bit[15:0] 00 00 hex automatic standard detection could not find a sound standard 00 02 hex msp standard codes (see table 3C8) ... 00 40 hex >07 ff hex automatic standard detection still active standard_res status 02 00 hex status register contains all user relevant internal information about the status of the msp bit[15:10] undefined bit[8] 0/1 1 indicates bilingual sound mode or sap present bit[7] 0/1 1 indicates independent mono sound (only for nicam on msp 4418g and msp 4458g) bit[6] 0/1 mono/stereo indication bit[5,9] 00 analog sound standard (fm or am) active 01 this pattern will not occur 10 digital sound (nicam) available (msp 4418g and msp 4458g only) 11 bad reception condition of digital sound (nicam) due to: a. high error rate b. unimplemented sound code c. data transmission only bit[4] 0/1 low/high level of digital i/o pin d_ctr_i/o_1 bit[3] 0/1 low/high level of digital i/o pin d_ctr_i/o_0 bit[2] 0 detected secondary carrier (2nd a2 or sap carrier) 1 no secondary carrier detected bit[1] 0 detected primary carrier (mono or mpx carrier) 1 no primary carrier detected bit[0] undefined if status change indication is activated by means of modus[1]: each change in the status register sets the digital i/o pin d_ctr_i/o_1 to high level. reading the status register resets d_ctr_i/o_1. status
msp 44x8g preliminary data sheet 26 micronas 3.3.2.5. write registers on i 2 c subaddress 12 hex table 3C11: write registers on i 2 c subaddress 12 hex register address function name preprocessing 00 0e hex fm/am prescale bit[15:8] 00 hex ... defines the input prescale gain for the demodulated fm or 7f hex am signal 00 hex off (reset condition) for all fm modes except satellite fm, the combinations of prescale value and fm deviation listed below lead to internal full scale. fm mode bit[15:8] 7f hex 28 khz fm deviation 48 hex 50 khz fm deviation 30 hex 75 khz fm deviation 24 hex 100 khz fm deviation 18 hex 150 khz fm deviation 13 hex 180 khz fm deviation (limit) fm high deviation mode (hdev2, msp standard code = c hex ) bit[15:8] 30 hex 150 khz fm deviation 14 hex 360 khz fm deviation (limit) fm very high deviation mode (hdev3, msp standard code = 6) bit[15:8] 20 hex 450 khz fm deviation 1a hex 540 khz fm deviation (limit) satellite fm with adaptive deemphasis bit[15:8] 10 hex recommendation am mode (msp standard code = 9) bit[15:8] 7c hex recommendation for sif input levels from 0.1 v pp to 0.8 v pp (due to the agc switched on, the am-output level remains stable and independent of the actual sif-level in the men- tioned input range) pre_fm
preliminary data sheet msp 44x8g micronas 27 (continued) 00 0e hex fm matrix modes defines the dematrix function for the demodulated fm signal bit[7:0] 00 hex no matrix (used for bilingual and unmatrixed stereo sound) 01 hex german stereo (standard b/g) 02 hex korean stereo (also used for btsc, eia-j, and fm radio) 03 hex sound a mono (left and right channel contain the mono sound of the fm/am mono carrier) 04 hex sound b mono (i.e. sap) in case of automatic sound select , the fm matrix mode is set automatically, i.e. the low-part of any i 2 c transmission to the register 00 0e hex is ignored. to enable a forced mono mode for all analog stereo systems by overriding the internal pilot or identification evaluation, the following steps must be transmitted: 1. modus with bit[0] = 0 (automatic sound select off) 2. fm presc./matrix with fm matrix = sound a mono (sap: sound b mono) 3. select fm/am source channel, with channel matrix set to stereo (transparent) fm_matrix 00 10 hex nicam prescale defines the input prescale value for the digital nicam signal bit[15:8] 00 hex ... 7f hex prescale gain examples: 00 hex off 20 hex 0db gain 5a hex 9 db gain (recommendation) 7f hex + 12 db gain (maximum gain) pre_nicam 00 16 hex 00 12 hex 00 11 hex i2s1 prescale i2s2 prescale i2s3 prescale defines the input prescale value for digital i 2 s input signals bit[15:8] 00 hex ... 7f hex prescale gain examples: 00 hex off 10 hex 0 db gain (recommendation) 7f hex + 18 db gain (maximum gain) pre_i2s1 pre_i2s2 pre_i2s3 00 0d hex scart input prescale defines the input prescale value for the analog scart input signal bit[15:8] 00 hex ... 7f hex prescale gain examples: 00 hex off 19 hex 0db gain (2 v rms input leads to digital full scale) 7f hex + 14 db gain (400 mv rms input leads to digital full scale) pre_scart table 3C11: write registers on i 2 c subaddress 12 hex , continued register address function name
msp 44x8g preliminary data sheet 28 micronas source select and output channel matrix 00 08 hex 00 09 hex 00 0a hex 00 41 hex 00 0b hex 00 0c hex 00 38 hex 00 39 hex source for: main output aux output scart1 da output scart2 da output i 2 s output quasi-peak detector mix1 input mix2 input bit[15:8] 0 fm/am: demodulated fm or am mono signal 1 stereo or a/b: demodulator stereo or a/b signal 3 stereo or a: demodulator stereo sound or language a (only defined for automatic sound select) 4 stereo or b: demodulator stereo sound or language b (only defined for automatic sound select) 2 scart input 5i 2 s1 input 6i 2 s2 input 7i 2 s3 input 15 mix output for demodulator sources, see table 2C2. src_main src_aux src_scart1 src_scart2 src_i2s src_qpeak src_mix1 src_mix2 00 08 hex 00 09 hex 00 0a hex 00 41 hex 00 0b hex 00 0c hex 00 38 hex 00 39 hex matrix mode for: main output aux output scart1 da output scart2 da output i 2 s output quasi-peak detector mix1 input mix2 input bit[7:0] 00 hex sound a mono (or left mono) 10 hex sound b mono (or right mono) 20 hex stereo (transparent mode) 30 hex mono (sum of left and right inputs divided by 2) more modes are listed in section 6.5.1. in automatic sound select mode, the demodulator source channels are set according to table 2C2. therefore, the matrix modes of the corresponding output channels should be set to stereo (transparent). mat_main mat_aux mat_scart1 mat_scart2 mat_i2s mat_qpeak mat_mix1 mat_mix2 table 3C11: write registers on i 2 c subaddress 12 hex , continued register address function name
preliminary data sheet msp 44x8g micronas 29 main and aux processing 00 00 hex 00 06 hex volume main volume aux bit[15:8] volume table with 1 db step size 7f hex + 12 db (maximum volume) 7e hex + 11 db ... 74 hex + 1db 73 hex 0db 72 hex - 1db ... 02 hex - 113 db 01 hex - 114 db 00 hex mute (reset condition) ff hex fast mute (needs about 75 ms until the signal is com- pletely ramped down) bit[7:5] higher resolution volume table 0 + 0db 1 + 0.125 db increase in addition to the volume table ... 7 + 0.875 db increase in addition to the volume table bit[4:0] not used must be set to 0 with large scale input signals, positive volume settings may lead to signal clipping. the msp 44x8g main and aux volume function is divided into a digital and an analog section. with fast mute, volume is reduced to mute position by digital vol- ume only. analog volume is not changed. this reduces any audible dc plops. to turn volume on again, the volume step that has been used before fast mute was activated must be transmitted. vol_main vol_aux 0029 hex automatic volume correction (avc) bit[15] 0 avc off, reset of internal variables 1avc on bit[14] 0 avc in main path 1 avc in mixer path bit[13:12] 0 must be set to zero bit[11:8] 8 8 s decay time 4 4 s decay time (recommended) 2 2 s decay time 1 20 ms decay time (should be used for approx. 100 ms after channel change) avc avc_decay 00 34 hex preemphasis aux channel bit[15:8] 00 hex preemphasis off 7f hex preemphasis 50 m s ( - 3 db scaling) ff hex preemphasis 75 m s ( - 3 db scaling) preemp_aux table 3C11: write registers on i 2 c subaddress 12 hex , continued register address function name
msp 44x8g preliminary data sheet 30 micronas scart output channel 00 07 hex 00 40 hex volume scart1 output channel volume scart2 output channel bit[15:8] volume table with 1 db step size 7f hex + 12 db (maximum volume) 7e hex + 11 db ... 74 hex + 1db 73 hex 0db 72 hex - 1db ... 02 hex - 113 db 01 hex - 114 db 00 hex mute (reset condition) bit[7:5] higher resolution volume table 0 + 0 db 1 + 0.125 db increase in addition to the volume table ... 7 + 0.875 db increase in addition to the volume table bit[4:0] 01 hex this must be 01 hex vol_scart1 vol_scart2 table 3C11: write registers on i 2 c subaddress 12 hex , continued register address function name
preliminary data sheet msp 44x8g micronas 31 scart switches and digital i/o pins 00 13 hex acb register defines the level of the digital output pins and the position of the scart switches bit[15] 0/1 low/high of digital output pin d_ctr_i/o_0 (modus[3]=0) bit[14] 0/1 low/high of digital output pin d_ctr_i/o_1 (modus[3]=0) bit[13:5] scart dsp input select xxxx00 xx0 scart1 to dsp input (reset position) xxxx01 xx0 mono to dsp input (sound a mono must be selected in the channel matrix mode for the corresponding output channels) xxxx10 xx0 scart2 to dsp input xxxx11 xx0 scart3 to dsp input xxxx00 xx1 scart4 to dsp input xxxx11 xx1 mute dsp input bit[13:5] scart1 output select xx00xx x0x scart3 input to scart1 output (reset position) xx01xx x0x scart2 input to scart1 output xx10xx x0x mono input to scart1 output xx11xx x0x scart1 da to scart1 output xx00xx x1x scart2 da to scart1 output xx01xx x1x scart1 input to scart1 output xx10xx x1x scart4 input to scart1 output xx11xx x1x mute scart1 output bit[13:5] scart2 output select 00xxxx 0xx scart1 da to scart2 output (reset position) 01xxxx 0xx scart1 input to scart2 output 10xxxx 0xx mono input to scart2 output 00xxxx 1xx scart2 da to scart2 output 01xxxx 1xx scart2 input to scart2 output 10xxxx 1xx scart3 input to scart2 output 11xxxx 1xx scart4 input to scart2 output 11xxxx 0xx mute scart2 output the reset position becomes active at the time of the first write transmission on the control bus to the audio processing part. by writing to the acb register first, the reset state can be redefined. acb_reg table 3C11: write registers on i 2 c subaddress 12 hex , continued register address function name
msp 44x8g preliminary data sheet 32 micronas mixing unit 00 3a hex 00 3b hex mix1 scale mix2 scale defines the input scale value for the digital mixing unit bit[15:8] 00 hex off 20 hex 50% ( - 6db gain) 40 hex 100% (0 db gain) 7f hex 200% (+6 db gain = maximum gain) note: if the sum of both mixing inputs exceeds 100%, clipping may occur in the successive processing. vol_mix1 vol_mix2 beeper 00 14 hex beeper volume and frequency bit[15:8] beeper volume 00 hex off 7f hex maximum volume bit[7:0] beeper frequency 01 hex 16 hz (lowest) 40 hex 1khz ff hex 4khz beeper table 3C11: write registers on i 2 c subaddress 12 hex , continued register address function name
preliminary data sheet msp 44x8g micronas 33 3.3.2.6. read registers on i 2 c subaddress 13 hex table 3C12: read registers on i 2 c subaddress 13 hex register address function name quasi-peak detector readout 00 19 hex 00 1a hex quasi-peak detector readout left quasi-peak detector readout right bit[15:0] 0 hex ... values are 16 bit twos complement (only positive) 7fff hex qpeak_l qpeak_r msp 44x8g version readout registers 001e hex msp hardware version code bit[15:8] 01 hex msp 44x8g- a 1 a change in the hardware version code defines hardware optimizations that may have influence on the chips behavior. the readout of this register is identi- cal to the hardware version code in the chips imprint. msp_hard msp family code bit[7:4] 1 hex msp 44 x8g-a1 msp_family msp major revision code bit[3:0] 7 hex msp 44x8 g -a1 msp_revision 001f hex msp product code bit[15:8] 08 hex msp 44 08 g-a1 12 hex msp 44 18 g-a1 1c hex msp 44 28 g-a1 30 hex msp 44 48 g-a1 3a hex msp 44 58 g-a1 by means of the msp-product code, the control processor is able to decide which tv sound standards have to be considered. msp_product msp rom version code bit[7:0] 41 hex msp 44x8g-a 1 a change in the rom version code defines internal software optimizations, that may have influence on the chips behavior, e.g. new features may have been included. while a software change is intended to create no compatibility prob- lems, customers that want to use the new functions can identify new msp 44x8g versions according to this number. msp_rom
msp 44x8g preliminary data sheet 34 micronas 3.4. programming tips this section describes the preferred method for initial- izing the msp 44x8g. the initialization is grouped into four sections: C scart signal path (analog signal path) C demodulator input C scart and i 2 s inputs C output channels see fig. 2C1 on page 8 for a complete signal flow. scart signal path 1. select analog input for the scart baseband pro- cessing (scart dsp input select) by means of the acb register. 2. select the source for each analog scart output (scart output select) by means of the acb regis- ter. demodulator input for a complete setup of the sound processing from analog if input to the source selection, the following steps must be performed: 1. set modus register to the preferred mode and sound if input. 2. write standard select register. 3. choose preferred prescale (fm and nicam) values. 4. if automatic sound select is not active: choose fm matrix repeatedly according to the sound mode indicated in the status register. scart and i 2 s inputs 1. select preferred prescale for scart. 2. select preferred prescale for i 2 s inputs (set to 0 db after reset). output channels 1. select the source channel and matrix for each out- put channel. 2. set audio baseband features (i.e. avc, 75 m s pre- emphasis) 3. select volume for each output channel. 3.5. examples of minimum initialization codes initialization of the msp 44x8g according to these list- ings reproduces sound of the selected standard on the main output. all numbers are hexadecimal. the exam- ples have the following structure: 1. perform an i 2 c controlled reset of the ic. 2. write modus register (with automatic sound select). 3. set source selection for main channel (with matrix set to stereo). 4. set prescale (fm and/or nicam and dummy fm matrix). 5. write standard select register. 6. set volume main channel to 0 db. 3.5.1. b/g-fm (a2 or nicam) <80008000> // softreset <80000000> <801000302003> // modus-register: automatic = on <801200080320> // source sel. = (st or a) & ch. matr. = st <8012000e2403> // fm/am-prescale = 24 hex , fm-matrix = mono/sounda <80120010005a> // nicam-prescale = 5a hex <801000200003> // standard select: a2 b/g or nicam b/g or <801000200008> <801200007300> // main volume 0 db 3.5.2. btsc-stereo <80008000> // softreset <80000000> <801000302003> // modus-register: automatic = on <801200080320> // source sel. = (st or a) & ch. matr. = st <8012000e2403> // fm/am-prescale = 24 hex , fm-matrix = sound a mono <801000200020> // standard select: btsc-stereo <801200007300> // main volume 0 db 3.5.3. btsc-sap with sap at main channel <80008000> // softreset <80000000> <801000302003> // modus-register: automatic = on <801200080420> // source sel. = (st or b) & ch. matr. = st <8012000e2403> // fm/am-prescale = 24 hex , fm-matrix = sound a mono <801000200021> // standard select: btsc-sap <801200007300> // main volume 0 db
preliminary data sheet msp 44x8g micronas 35 3.5.4. fm-stereo radio <80008000> // softreset <80000000> <801000302003> // modus-register: automatic = on <801200080320> // source sel. = (st or a) & ch. matr. = st <8012000e2403> // fm/am-prescale = 24 hex , fm-matrix = sound a mono <801000200040> // standard select: fm-stereo-radio <801200007300> // main volume 0 db 3.5.5. automatic standard detection a detailed software flow diagram is shown in fig. 3C2 on page 36. <80008000> // softreset <80000000> <801000302003> // modus-register: automatic = on <801200080320> // source sel. = (st or a) & ch. matr. = st <8012000e2403> // fm/am-prescale = 24 hex , fm-matrix = sound a mono <80120010005a> // nicam-prescale = 5a hex <801000200001> // standard select: automatic standard detection // wait till standard result contains a value 07ff // if standard result contains 0000 // do some error handling // else <801200007300> // main volume 0 db 3.5.6. software flow for interrupt driven status check a detailed software flow diagram is shown in fig. 3C2 on page 36. if the d_ctr_i/o_1 pin of the msp 44x8g is con- nected to an interrupt input pin of the controller, the fol- lowing interrupt handler can be applied to be automati- cally called with each status change of the msp 44x8g. the interrupt handler may adjust the dis- play according to the new status information. interrupt handler: <80 11 02 00 <81 dd dd> // read status // adjust display with given status information // return from interrupt
msp 44x8g preliminary data sheet 36 micronas fig. 3C2: software flow diagram for a minimum demodulator setup for a european multistandard set applying the automatic sound select feature write source select settings example: set main source select to "stereo or a" set aux source select to "stereo or b" set scart_out source select to "stereo or a/b" set channel matrix mode for all outputs to "stereo" write 01 into standard select register (start automatic standard detection) write modus register : example for the essential bits: [0] = 1 automatic sound select = on [1] = 1 enable interrupt if status changes [8] = 0 ana_in1+ is selected define preference for automatic standard detection: [12] = 0 if 6.5 mhz, set secam-l [14:13] = 3 ignore 4.5 mhz carrier write fm/am-prescale write nicam-prescale in case of interrupt from msp to controller: read status adjust display if bilingual, adjust source select setting if required result = 0 ? set previous standard or set standard manually according picture information yes no expecting interrupt from msp
preliminary data sheet msp 44x8g micronas 37 4. specifications 4.1. outline dimensions fig. 4C1: 80-pin plastic quad flat pack (pqfp80) weight approximately 1.61 g dimensions in mm fig. 4C2: 64-pin plastic low-profile quad flat pack (plqfp64) weight approximately 0.35 g dimensions in mm 15 x 0.8 = 12.0 0.1 8 9.8 1.8 16 5 8 10.3 0.8 0.8 41 64 24 1 65 80 40 25 1.8 0.1 3 0.2 spgs705000-1(p80)/1e 23.2 0.15 17.2 0.15 20 0.1 14 0.1 23 x 0.8 = 18.4 0.1 0.17 0.04 0.37 0.05 1.3 0.05 2.7 0.1 10 0.1 1.75 1.75 49 64 116 17 32 33 48 d0025/3e 0.5 0.5 0.1 12 0.2 1.5 0.1 1.4 0.05 12 0.2 10 0.1 0.145 0.055 0.22 0.05 15 x 0.5 = 7.5 0.1 15 x 0.5 = 7.5 0.1
msp 44x8g preliminary data sheet 38 micronas fig. 4C3: 64-pin plastic shrink dual-inline package (psdip64) weight approximately 9.0 g dimensions in mm 132 33 64 57.7 0.1 0.8 0.2 3.8 0.1 3.2 0.2 1.778 1 0.05 31 x 1.778 = 55.1 0.1 0.48 0.06 20.3 0.5 0.28 0.06 18 0.05 19.3 0.1 spgs0016-5(p64)/1e
preliminary data sheet msp 44x8g micronas 39 4.2. pin connections and short descriptions nc = not connected ( leave vacant for future compatibility reasons) tp = test pin ( leave vacant - pin is used for production test only) lv = leave vacant x = obligatory; connect as described in application circuit diagram pin no. pin name type connection (if not used) short description pqfp 80-pin plqfp 64-pin psdip 64-pin 1 64 8 nc lv not connected 219i2c_cl in/outx i 2 c clock 3 2 10 i2c_da in/out x i 2 c data 4 3 11 i2s_cl in/out lv i 2 s clock 5 4 12 i2s_ws in/out lv i 2 s word strobe 6 5 13 i2s_da_out out lv i 2 s data output 7 6 14 i2s_da_in1 in lv i 2 s1 data input 8 7 15 adr_da out lv adr data output 9 8 16 adr_ws out lv adr word strobe 10 9 17 adr_cl out lv adr clock 11 -- dvsup x digital power supply + 5 v 12 -- dvsup x digital power supply + 5 v 13 10 18 dvsup x digital power supply + 5 v 14 -- dvss x digital ground 15 -- dvss x digital ground 16 11 19 dvss x digital ground - 12 20 i2s_da_in2/3 in lv i 2 s2/3-data input 17 -- i2s_da_in2 in lv pqfp80: pin 22 separate i2s_da_in3 18 13 21 nc lv not connected 19 14 22 i2s_cl3 in lv i 2 s3 clock 20 15 23 i2s_ws3 in lv i 2 s3 word strobe 21 16 24 resetq in x power-on-reset 22 -- i2s_da_in3 in lv i 2 s3-data input 23 -- nc lv not connected 24 17 25 daca_r out lv aux out, right 25 18 26 daca_l out lv aux out, left 26 19 27 vref2 x reference ground 2
msp 44x8g preliminary data sheet 40 micronas 27 20 28 dacm_r out lv main out, right 28 21 29 dacm_l out lv main out, left 29 22 30 nc lv not connected 30 23 31 nc lv not connected 31 24 32 nc lv not connected 32 -- nc lv not connected 33 25 33 sc2_out_r out lv scart output 2, right 34 26 34 sc2_out_l out lv scart output 2, left 35 27 35 vref1 x reference ground 1 36 28 36 sc1_out_r out lv scart output 1, right 37 29 37 sc1_out_l out lv scart output 1, left 38 30 38 capl_a x volume capacitor aux 39 31 39 ahvsup x analog power supply 8.0 v 40 32 40 capl_m x volume capacitor main 41 -- nc lv not connected 42 -- nc lv not connected 43 -- ahvss x analog ground 44 33 41 ahvss x analog ground 45 34 42 agndc x analog reference voltage 46 -- nc lv not connected 47 35 43 sc4_in_l in lv scart 4 input, left 48 36 44 sc4_in_r in lv scart 4 input, right 49 37 45 asg ahvss analog shield ground 50 38 46 sc3_in_l in lv scart 3 input, left 51 39 47 sc3_in_r in lv scart 3 input, right 52 40 48 asg ahvss analog shield ground 53 41 49 sc2_in_l in lv scart 2 input, left 54 42 50 sc2_in_r in lv scart 2 input, right 55 43 51 asg ahvss analog shield ground 56 44 52 sc1_in_l in lv scart 1 input, left 57 45 53 sc1_in_r in lv scart 1 input, right pin no. pin name type connection (if not used) short description pqfp 80-pin plqfp 64-pin psdip 64-pin
preliminary data sheet msp 44x8g micronas 41 58 46 54 vreftop x reference voltage if a/d converter 59 -- nc lv not connected 60 47 55 mono_in in lv mono input 61 -- avss x analog ground 62 48 56 avss x analog ground 63 -- nc lv not connected 64 -- nc lv not connected 65 -- avsup x analog power supply + 5v 66 49 57 avsup x analog power supply + 5v 67 50 58 ana_in1 + in lv if input 1 68 51 59 ana_in - in avss via 56 pf / lv if common (can be left vacant, only if if input 1 is also not in use) 69 52 60 ana_in2 + in avss via 56 pf / lv if input 2 (can be left vacant, only if if input 1 is also not in use) 70 53 61 testen in avss test pin 71 54 62 xtal_in in x crystal oscillator 72 55 63 xtal_out out x / lv crystal oscillator (see also section 4.3. pin descriptions on page 42) 73 56 64 tp lv test pin 74 57 1 aud_cl_out out lv audio clock output (18.432 mhz) 75 58 2 nc lv not connected 76 59 3 nc lv not connected 77 60 4 d_ctr_i/o_1 in/out lv d_ctr_i/o_1 78 61 5 d_ctr_i/o_0 in/out lv d_ctr_i/o_0 79 62 6 adr_sel in x i 2 c bus address select 80 63 7 standbyq in x stand-by (low-active) pin no. pin name type connection (if not used) short description pqfp 80-pin plqfp 64-pin psdip 64-pin
msp 44x8g preliminary data sheet 42 micronas 4.3. pin descriptions pin numbers refer to the 80-pin pqfp package. pin 1, nc C pin not connected. pin 2, i2c_cl C i 2 c clock input/output (fig. 4C8) via this pin, the i 2 c-bus clock signal has to be sup- plied. the signal can be pulled down by the msp in case of wait conditions. pin 3, i2c_da C i 2 c data input/output (fig. 4C8) via this pin, the i 2 c-bus data is written to or read from the msp. pin 4, i2s_cl C i 2 s clock input/output (fig. 4C11) clock line for the synchronous i 2 s bus. in master mode, this line is driven by the msp; in slave mode, an external i 2 s clock has to be supplied. pin 5, i2s_ws C i 2 s word strobe input/output (fig. 4C11) word strobe line for the synchronous i 2 s bus. in mas- ter mode, this line is driven by the msp; in slave mode, an external i 2 s word strobe has to be supplied. pin 6, i2s_da_out1 C i 2 s data output (fig. 4C7) output of digital serial sound data of the msp on the synchronous i 2 s bus. pin 7, i2s_da_in1 C i 2 s data input 1 (fig. 4C9) first input of digital serial sound data to the msp via the synchronous i 2 s bus. pin 8, adr_da C adr bus data output (fig. 4C7) output of digital serial data to the drp 3510a via the adr bus. pin 9, adr_ws C adr bus word strobe output (fig. 4C7) word strobe output for the adr bus. pin 10, adr_cl C adr bus clock output (fig. 4C7) clock line for the adr bus. pins 11, 12, 13, dvsup* C digital supply voltage power supply for the digital circuitry of the msp. must be connected to a + 5 v power supply. pins 14, 15, 16, dvss* C digital ground ground connection for the digital circuitry of the msp. pin 17, i2s_da_in2 C i 2 s data input 2 (fig. 4C9) second input of digital serial sound data to the msp via the synchronous i 2 s bus. in all packages except pqfp80, this pin is also connected to the asynchro- nous i 2 s interface 3. pins 18, nc C pin not connected. pins 19, i2s_cl3 C i 2 s clock input (fig. 4C9) clock line for the asynchronous i 2 s bus. since only a slave mode is available an external i 2 s clock has to be supplied. pins 20, i2s_ws3 C i 2 s word strobe input (fig. 4C9) word strobe line for the asynchronous i 2 s bus. since only a slave mode is available an external i 2 s word strobe has to be supplied. pin 21, resetq C reset input (fig. 4C9) in the steady state, high level is required. a low level resets the msp 44x8g. pin 22, i2s_da_in3 C i 2 s data input 3 (fig. 4C9) input of digital serial sound data to the msp via the asynchronous i 2 s bus. in all packages except pqfp80, this pin is also connected to synchronous i 2 s interface 2. pins 23, nc C pin not connected. pins 24, 25, daca_r/l C aux outputs (fig. 4C17) output of the aux signal. a 1 nf capacitor to ahvss must be connected to these pins. the dc offset on these pins depends on the selected aux volume. pin 26, vref2 C reference ground 2 reference analog ground. this pin must be connected separately to the ground (ahvss). vref2 serves as a clean ground and should be used as the reference for analog connections to the main and aux outputs. pins 27, 28, dacm_r/l C main outputs (fig. 4C17) output of the main signal. a 1 nf capacitor to ahvss must be connected to these pins. the dc offset on these pins depends on the selected main volume. pin 29, 30, 31, 32 nc C pin not connected. pins 33, 34, sc2_out_r/l C scart2 outputs (fig. 4C19) output of the scart2 signal. connections to these pins must use a 100- w series resistor and are intended to be ac-coupled. pin 35, vref1 C reference ground 1 reference analog ground. this pin must be connected separately to the ground (ahvss). vref1 serves as a clean ground and should be used as the reference for analog connections to the scart outputs. pins 36, 37, sc1_out_r/l C scart1 outputs (fig. 4C19) output of the scart1 signal. connections to these pins must use a 100- w series resistor and are intended to be ac-coupled.
preliminary data sheet msp 44x8g micronas 43 pin 38, capla C volume capacitor aux (fig. 4C14) a 10- m f capacitor to ahvsup must be connected to this pin. it serves as a smoothing filter for aux volume changes in order to suppress audible plops. the value of the capacitor can be lowered to 1- m f if faster response is required. the area encircled by the trace lines should be minimized; keep traces as short as possible. this input is sensitive for magnetic induction. pin 39, ahvsup* C analog power supply high volt- age power is supplied via this pin for the analog circuitry of the msp (except if input). this pin must be connected to the + 8 v supply. (+5 v-operation is possible with restrictions in performance) pin 40, caplm C volume capacitor main (fig. 4C14) a 10- m f capacitor to ahvsup must be connected to this pin. it serves as a smoothing filter for main volume changes in order to suppress audible plops. the value of the capacitor can be lowered to 1 m f if faster response is required. the area encircled by the trace lines should be minimized; keep traces as short as possible. this input is sensitive for magnetic induction. pins 41, 42, nc C pins not connected. pins 43, 44, ahvss* C analog power supply high voltage ground connection for the analog circuitry of the msp (except if input). pin 45, agndc C internal analog reference voltage this pin serves as the internal ground connection for the analog circuitry (except if input). it must be con- nected to the vref pins with a 3.3- m f and a 100-nf capacitor in parallel. this pins shows a dc level of typ- ically 3.73 v. pin 46, nc C pin not connected. pins 47, 48, sc4_in_l/r C scart4 inputs (fig. 4C16) the analog input signal for scart4 is fed to this pin. analog input connection must be ac-coupled. pins 49, 52, and 55, asg* C analog shield ground analog ground (ahvss) should be connected to this pin to reduce cross-coupling between scart inputs. pins 50, 51, sc3_in_l/r C scart3 inputs (fig. 4C16) the analog input signal for scart3 is fed to this pin. analog input connection must be ac-coupled. pins 53, 54 sc2_in_l/r C scart2 inputs (fig. 4C16) the analog input signal for scart2 is fed to this pin. analog input connection must be ac-coupled. pins 56, 57 sc1_in_l/r C scart1 inputs (fig. 4C16) the analog input signal for scart1 is fed to this pin. analog input connection must be ac-coupled. pin 58, vreftop C reference voltage if a/d con- verter (fig. 4C13) via this pin, the reference voltage for the if a/d con- verter is decoupled. it must be connected to avss pins with a 10- m f and a 100-nf capacitor in parallel. traces must be kept short. pin 59, nc C pin not connected. pin 60 mono_in C mono input (fig. 4C16) the analog mono input signal is fed to this pin. analog input connection must be ac-coupled. pins 61, 62, avss* C analog power supply voltage ground connection for the analog if input circuitry of the msp. pins 63, 64, nc C pins not connected. pins 65, 66, avsup* C analog power supply voltage power is supplied via this pin for the analog if input cir- cuitry of the msp. this pin must be connected to the + 5v supply. pin 67, ana_in1 + C if input 1 (fig. 4C13) the analog sound if signal is supplied to this pin. inputs must be ac-coupled. this pin is designed as symmetrical input: ana_in1 + is internally connected to one input of a symmetrical op amp, ana_in- to the other. pin 68, ana_in - C if common (fig. 4C13) this pins serves as a common reference for ana_in1/ 2 + inputs and must be ac-coupled. pin 69, ana_in2 + C if input 2 (fig. 4C13) the analog sound if signal is supplied to this pin. inputs must be ac-coupled. this pin is designed as symmetrical input: ana_in2 + is internally connected to one input of a symmetrical op amp, ana_in - to the other. pin 70, testen C test enable pin (fig. 4C9) this pin enables factory test modes. for normal opera- tion, it must be connected to ground.
msp 44x8g preliminary data sheet 44 micronas pins 71, 72 xtal_in, xtal_out C crystal input and output pins (fig. 4C12) these pins are connected to an 18.432 mhz crystal oscillator which is digitally tuned by integrated capaci- tances. an external clock can be fed into xtal_in (leave xtal_out vacant in this case). the audio clock output signal aud_cl_out is derived from the oscillator. external capacitors at each crystal pin to ground (avss) are required. it should be verified by layout, that no supply current for the digital circuitry is flowing through the ground connection point. pin 73, tp C this pin enables factory test modes. for normal operation, it must be left vacant. pin 74, aud_cl_out C audio clock output (fig. 4C12) this is the 18.432 mhz main clock output. pins 75, 76, nc C pins not connected. pins 77, 78, d_ctr_i/o_1/0 C digital control input/ output pins (fig. 4C11) these pins serve as general purpose input/output pins. pin d_ctr_i/o_1 can be used as an interrupt request pin to the controller. pin 79, adr_sel C i 2 c bus address select (fig. 4C10) by means of this pin, one of three device addresses for the msp can be selected. the pin can be connected to ground (i 2 c device addresses 80/81 hex ), to + 5 v sup- ply (84/85 hex ), or left open (88/89 hex ). pin 80, standbyq C stand-by in normal operation, this pin must be high. if the msp is switched off by first pulling standbyq low and then (after >1 m s delay) switching off the 5 v, but keeping the 8-v power supply ( stand-by-mode ), the scart switches maintain their position and function. pin -, i2s_da_in2/3 - i 2 s data input (see fig. 4C9). this pin is connected to i2s_da_in2 and i2s_da_in3. not available for pqfp80-pin package. * application note: all ground pins should be connected to one low-resis- tive ground plane. all supply pins should be connected separately with short and low-resistive lines to the power supply. decoupling capacitors from dvsup to dvss, avsup to avss, and ahvsup to ahvss are recommended as closely as possible to these pins. decoupling of dvsup and dvss is most important. we recommend using more than one capacitor. by choosing different values, the frequency range of active decoupling can be extended. in our application boards we use: 220 pf, 470 pf, 1.5 nf, and 10 m f. the capacitor with the low- est value should be placed nearest to the pins. the asg pins should be connected as closely as pos- sible to the msp ground. they are intended for leading with the scart signals as shield lines and should not be connected to ground at the scart-connector.
preliminary data sheet msp 44x8g micronas 45 4.4. pin configurations fig. 4C4: 80-pin pqfp package 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 101112131415161718192021222324 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 avsup avsup ana_in1+ ana_in - ana_in2+ testen xtal_in xtal_out tp aud_cl_out nc nc d_ctr_i/o_1 d_ctr_i/o_0 adr_sel standbyq capl_m ahvsup capl_a sc1_out_l sc1_out_r vref1 sc2_out_l sc2_out_r nc nc nc nc dacm_l dacm_r vref2 daca_l nc avss avss mono_in nc vreftop sc1_in_r sc1_in_l asg nc sc2_in_r sc2_in_l asg sc3_in_r sc3_in_l asg sc4_in_r sc4_in_l nc agndc ahvss ahvss nc nc i2c_cl i2c_da i2s_cl i2s_ws i2s_da_out i2s_da_in1 adr_da adr_ws adr_cl nc dvsup dvsup dvsup dvss dvss dvss i2s_da_in2 nc i2s_cl3 i2s_ws3 resetq i2s_da_in3 nc daca_r msp 44x8g
msp 44x8g preliminary data sheet 46 micronas fig. 4C5: 64-pin plqfp package 49 avsup 50 ana_in1+ 51 ana_in - 52 ana_in2+ 53 testen 54 xtal_in 55 xtal_out 56 tp 57 aud_cl_out 58 nc 59 nc 60 d_ctr_i/o_1 61 c_ctr_i/o_0 62 adr_sel 63 standbyq 64 nc capl_m 32 ahvsup 31 capl_a 30 sc1_out_l 29 sc1_out_r 28 vref1 27 sc2_out_l 26 sc2_out_r 25 nc 24 nc 23 nc 22 dacm_l 21 dacm_r 20 vref2 19 daca_l 18 daca_r 17 mono_in vreftop sc1_in_r sc1_in_l asg sc2_in_r sc2_in_l avss asg sc3_in_r sc3_in_l asg sc4_in_r sc4_in_l agndc ahvss i2c_da i2s_cl i2s_ws i2s_da_out i2s_da_in1 adr_da adr_ws i2c_cl adr_cl dvsup dvss i2s_da_in2/3 nc i2s_cl3 i2s_ws3 resetq 12345678910111213141516 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 msp 44x8g
preliminary data sheet msp 44x8g micronas 47 fig. 4C6: 64-pin psdip package 1 aud_cl_out 2 nc 3 nc 4 d_ctr_i/o_1 5 d_ctr_i/o_0 6 adr_sel 7 standbyq 8 nc 9 i2c_cl 10 i2c_da 11 i2s_cl 12 i2s_ws 13 i2s_da_out 14 i2s_da_in1 15 adr_da 16 adr_ws tp 64 xtal_out 63 xtal_in 62 testen 61 ana_in2+ 60 ana_in - 59 ana_in+ 58 avsup 57 avss 56 mono_in 55 vreftop 54 sc1_in_r 53 sc1_in_l 52 asg 51 sc2_in_r 50 sc2_in_l 49 17 adr_cl 18 dvsup 19 dvss 20 i2s_da_in2/3 21 nc 22 i2s_cl3 23 i2s_ws3 24 resetq 25 daca_r 26 daca_l asg 48 sc3_in_r 47 sc3_in_l 46 asg 45 sc4_in_r 44 sc4_in_l 43 agndc 42 ahvss 41 capl_m 40 ahvsup 39 msp 44x8g vref2 dacm_r dacm_l nc nc nc 38 37 36 35 34 33 27 28 29 30 31 32 capl_a sc1_out_l sc1_out_r vref1 sc2_out_l sc2_out_r
msp 44x8g preliminary data sheet 48 micronas 4.5. pin circuits pin numbers refer to the pqfp80 package. fig. 4C7: output pins 6, 8, 9, and 10 (i2s_da_out, adr_da, adr_ws, adr_cl) fig. 4C8: input/output pins 2 and 3 (i2c_cl, i2c_da) fig. 4C9: input pins 7, 17, 22, 19, 20, 21, 70, and 80 (i2s_da_in1..3, i2s_cl3, i2s_ws3, resetq, testen, standbyq ) fig. 4C10: input pin 79 (adr_sel) fig. 4C11: input/output pins 4, 5, 77, and 78 (i2s_cl, i2s_ws, d_ctr_i/o_1, d_ctr_i/o_0) fig. 4C12: output/input pins 71, 72, and 74 (xtal_in, xtal_out, aud_cl_out) fig. 4C13: input pins 58, 67, 68, and 69 (vreftop, ana_in1 + , ana_in-, ana_in2 + ) dvsup p n gnd n gnd adr_sel gnd dvsup 23 k w 23 k w dvsup p n gnd 3 - 30 pf 2.5 v 500 k w 3 - 30 pf p n gain=0.5 d a ana_in1+ vreftop ana_in - ana_in2+
preliminary data sheet msp 44x8g micronas 49 fig. 4C14: capacitor pins 38 and 40 (capl_a, capl_m) fig. 4C15: input pin 60 (mono_in ) fig. 4C16: input pins 47, 48, 50, 51, 53, 54, 56, and 57 (sc4-1_in_l/r) fig. 4C17: output pins 24, 25, 27, and 28 (daca_r/l, dacm_r/l) fig. 4C18: pin 45 (agndc) fig. 4C19: output pins 33, 34, 36, and 37 (sc_2_out_r/l, sc_1_out_r/l) 0...2 v ? 3.75 v 24 k w ? 3.75 v 40 k w ahvsup 0...1.2 ma 3.3 k w ? 3.75 v 125 k w 26 pf 120 k w 300 w ? 3.75 v
msp 44x8g preliminary data sheet 50 micronas 4.6. electrical characteristics 4.6.1. absolute maximum ratings stresses beyond those listed in the absolute maximum ratings may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions/characteristics of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. symbol parameter pin name min. max. unit t a ambient operating temperature - 070 1) c t s storage temperature -- 40 125 c v sup1 first supply voltage ahvsup - 0.3 9.0 v v sup2 second supply voltage dvsup - 0.3 6.0 v v sup3 third supply voltage avsup - 0.3 6.0 v dv sup23 voltage between avsup and dvsup avsup, dvsup - 0.5 0.5 v p tot package power dissipation psdip64 plqfp64 pqfp80 ahvsup, dvsup, avsup 1300 960 1000 mw mw mw v idig input voltage, all digital inputs - 0.3 v sup2 + 0.3 v i idig input current, all digital pins - 20 + 20 ma 2) v iana input voltage, all analog inputs scn_in_s, 3) mono_in - 0.3 v sup1 + 0.3 v i iana input current, all analog inputs scn_in_s, 3) mono_in - 5 + 5ma 2) i oana output current, all scart outputs scn_out_s 3) 4) , 5) 4) , 5) i oana output current, all analog outputs except scart outputs dacp_s 3) 4) 4) i cana output current, other pins connected to capacitors capl_p, 3) agndc 4) 4) 1) plqfp64: 65 c 2) positive value means current flowing into the circuit 3) n means 1, 2, 3, or 4, s means l or r, p means m or a 4) the analog outputs are short-circuit proof with respect to first supply voltage and ground. 5) total chip power dissipation must not exceed absolute maximum rating.
preliminary data sheet msp 44x8g micronas 51 4.6.2. recommended operating conditions (t a = 0 to 70 c) 4.6.2.1. general recommended operating conditions 4.6.2.2. analog input and output recommendations symbol parameter pin name min. typ. max. unit v sup1 first supply voltage (8-v operation) ahvsup 7.6 8.0 8.7 v first supply voltage (5-v operation) 4.75 5.0 5.25 v v sup2 second supply voltage (5-v operation) dvsup 4.75 5.0 5.25 v second supply voltage (3.3-v operation) 3.15 3.3 3.45 v v sup3 third supply voltage avsup 4.75 5.0 5.25 v t stbyq1 standbyq setup time before turn-off of second supply voltage standbyq, dvsup 1 m s symbol parameter pin name min. typ. max. unit c agndc agndc-filter-capacitor agndc - 20% 3.3 m f ceramic capacitor in parallel - 20% 100 nf c insc dc-decoupling capacitor in front of scart inputs scn_in_s 1) - 20% 330 nf v insc scart input level 2.0 v rms v inmono input level, mono input mono_in 2.0 v rms r lsc scart load resistance scn_out_s 1) 10 k w c lsc scart load capacitance 6.0 nf c vma main/aux volume capacitor capl_m, capl_a 10 m f c fma main/aux filter capacitor dacm_s, daca_s 1) - 10% 1 + 10% nf 1) n means 1, 2, or 3, s means l or r, p means m or a
msp 44x8g preliminary data sheet 52 micronas 4.6.2.3. recommendations for analog sound if input signal symbol parameter pin name min. typ. max. unit c vreftop vreftop-filter-capacitor vreftop - 20 % 10 m f ceramic capacitor in parallel - 20 % 100 nf f if_fmtv analog input frequency range for tv applications ana_in1 + , ana_in2 + , ana_in - 09mhz f if_fmradio analog input frequency for fm-radio applications 10.7 mhz v if_fm analog input range fm/nicam 0.1 0.8 3 v pp v if_am analog input range am/nicam 0.1 0.45 0.8 v pp r fmni ratio: nicam carrier/fm carrier (unmodulated carriers) bg: i: - 20 - 23 - 7 - 10 0 0 db db r amni ratio: nicam carrier/am carrier (unmodulated carriers) - 25 - 11 0 db r fm ratio: fm-main/fm-sub satellite 7 db r fm1/fm2 ratio: fm1/fm2 german fm-system 7db r fc ratio: main fm carrier/ color carrier 15 -- db r fv ratio: main fm carrier/ luma components 15 -- db pr if passband ripple -- 2db sup hf suppression of spectrum above 9.0 mhz (not for fm radio) 15 db fm max maximum fm-deviation (approx.) normal mode hdev2: high deviation mode hdev3: very high deviation mode 180 360 540 khz khz khz
preliminary data sheet msp 44x8g micronas 53 4.6.2.4. crystal recommendations symbol parameter pin name min. typ. max. unit general crystal recommendations f p crystal parallel resonance fre- quency at 12 pf load capacitance 18.432 mhz r r crystal series resistance 8 25 w c 0 crystal shunt (parallel) capacitance 6.2 7.0 pf c l external load capacitance 1) xtal_in, xtal_out psdip approx. 1.5 p(l)qfp approx. 3.3 pf pf crystal recommendations for master-slave applications (msp-clock must perform synchronization to i 2 s clock) f tol accuracy of adjustment - 20 + 20 ppm d tem frequency variation versus temperature - 20 + 20 ppm c 1 motional (dynamic) capacitance 19 24 ff f cl required open loop clock frequency (t amb = 25 c) aud_cl_out 18.431 18.433 mhz crystal recommendations for fm / nicam applications (no msp-clock synchronization to i 2 s clock possible) f tol accuracy of adjustment - 30 + 30 ppm d tem frequency variation versus temperature - 30 + 30 ppm c 1 motional (dynamic) capacitance 15 ff f cl required open loop clock frequency (t amb = 25 c) aud_cl_out 18.4305 18.4335 mhz crystal recommendations for all analog fm/am applications (no msp-clock synchronization to i 2 s clock possible) f tol accuracy of adjustment - 100 + 100 ppm d tem frequency variation versus temperature - 50 + 50 ppm f cl required open loop clock frequency (t amb = 25 c) aud_cl_out 18.429 18.435 mhz amplitude recommendation for operation with external clock input (c load after reset typ. 22 pf) v xca external clock amplitude xtal_in 0.7 v pp 1) external capacitors at each crystal pin to ground are required. they are necessary to tune the open-loop fre- quency of the internal pll and to stabilize the frequency in closed-loop operation. due to different layouts, the accurate capacitor size should be determined with the customer pcb . the sug- gested values (1.5...3.3 pf) are figures based on experience and should serve as start value. to define the capacitor size, reset the msp without transmitting any further i2c telegrams. measure the fre- quency at aud_cl_out-pin. change the capacitor size until the free running frequency matches 18.432 mhz as closely as possible. the higher the capacity, the lower the resulting clock frequency.
msp 44x8g preliminary data sheet 54 micronas 4.6.3. characteristics at t a = 0 to 70 c, f clock = 18.432 mhz, v sup1 = 7.6 to 8.7 v, v sup2 = 4.75 to 5.25 v for min./max. values at t a = 60 c, f clock = 18.432 mhz, v sup1 = 8 v, v sup2 = 5 v for typical values, t j = junction temperature main (m) = main channel, aux (a) = aux channel 4.6.3.1. general characteristics symbol parameter pin name min. typ. max. unit test conditions supply i sup1a first supply current (active) (8-v operation) analog volume for main and aux at 0 db analog volume for main and aux at - 30 db ahvsup 18 12 25 17 ma ma first supply current (active) (5-v operation) analog volume for main and aux at 0 db analog volume for main and aux at - 30 db 12 8 17 11 ma ma i sup2a second supply current (active) (5-v operation) dvsup 70 85 ma second supply current (active) (3.3-v operation) 60 75 ma i sup3a third supply current (active) avsup 35 45 ma i sup1s first supply current (8-v operation) (standby mode) at t j = 27 c ahvsup 5.6 7.7 ma standbyq = low first supply current (5-v operation) (standby mode) at t j = 27 c 3.7 5.1 ma standbyq = low clock f clock clock input frequency xtal_in 18.432 mhz d clock clock high to low ratio 45 55 % t jitter clock jitter (verification not provided in production test) 50 ps v xtaldc dc-voltage oscillator 2.5 v t startup oscillator startup time at vdd slew-rate of 1 v/ m s xtal_in, xtal_out 0.4 2 ms v aclkac audio clock output ac voltage aud_cl_out 1.2 1.8 v pp load = 40 pf v aclkdc audio clock output dc voltage 0.4 0.6 v sup3 i max = 0.2 ma r outhf_acl hf output resistance 140 w
preliminary data sheet msp 44x8g micronas 55 4.6.3.2. digital inputs, digital outputs symbol parameter pin name min. typ. max. unit test conditions digital inputs levels v digil digital input low voltage standbyq d_ctr_i/o_0/1 0.2 v sup2 v digih digital input high voltage 0.5 v sup2 z digi input impedance 5 pf i dleak digital input leakage current - 11 m a0v < u input < dvsup d_ctr_i/o_0/1: tri-state v digil adr_sel input low voltage adr_sel 0.2 v sup2 v digih adr_sel input high voltage 0.8 v sup2 i adrsel input current - 500 - 220 m au adr_sel = dvss 220 500 m au adr_sel = dvsup digital output levels v dctrol digital output low voltage d_ctr_i/o_0 d_ctr_i/o_1 0.4 v iddctr = 1 ma v dctroh digital output high voltage v sup2 - 0.3 v iddctr = - 1 ma
msp 44x8g preliminary data sheet 56 micronas 4.6.3.3. reset input and power-up fig. 4C20: power-up sequence symbol parameter pin name min. typ. max. unit test conditions resetq input levels v rhl reset high-low transition voltage resetq 0.45 0.55 v sup2 v rlh reset low-high transition voltage 0.7 0.8 v sup2 z res input impedance 5 pf i res input pin leakage current -1 1 m a0v < u input < dvsup v sup2 - 10% internal reset t/ms resetq avsup dvsup high low t/ms t/ms low-to-high threshold high-to-low threshold reset delay >2 ms note: the reset should not reach high level before the oscillator has started. this requires a reset delay of >2 ms 0.7 x v sup2 means 3.5 volt with v sup2 = 5.0 v 0.7 v sup2 0.45...0.55 v sup2
preliminary data sheet msp 44x8g micronas 57 4.6.3.4. i 2 c-bus characteristics fig. 4C21: i 2 c bus timing diagram symbol parameter pin name min. typ. max. unit test conditions v i2cil i 2 c-bus input low voltage i2c_cl, i2c_da 0.3 v sup2 v i2cih i 2 c-bus input high voltage 0.6 v sup2 t i2c1 i 2 c start condition setup time 120 ns t i2c2 i 2 c stop condition setup time 120 ns t i2c5 i 2 c-data setup time before rising edge of clock 55 ns t i2c6 i 2 c-data hold time after falling edge of clock 55 ns t i2c3 i 2 c-clock low pulse time i2c_cl 500 ns t i2c4 i 2 c-clock high pulse time 500 ns f i2c i 2 c-bus frequency 1.0 mhz v i2col i 2 c-data output low voltage i2c_cl, i2c_da 0.4 v i i2col = 3 ma i i2coh i 2 c-data output high leakage current 1.0 m av i2coh = 5 v t i2col1 i 2 c-data output hold time after falling edge of clock 15 ns t i2col2 i 2 c-data output setup time before rising edge of clock 100 ns f i2c = 1 mhz i2c_cl i2c_da as input i2c_da as output t i2c1 t i2c5 t i2c6 t i2c2 t i2c4 t i2c3 1/f i2c t i2col2 t i2col1
msp 44x8g preliminary data sheet 58 micronas 4.6.3.5. i 2 s-bus characteristics symbol parameter pin name min. typ. max. unit test conditions v i2sil input low voltage i2s_cl i2s_ws i2s_cl3 i2s_ws3 i2s_da_in1..3 0.2 v sup2 v i2sih input high voltage 0.5 v sup2 z i2si input impedance 5 pf i leaki2s input leakage current - 11 m a0v < u input < dvsup v i2sol i 2 s output low voltage i2s_cl i2s_ws i2s_da_out 0.4 v i i2sol = 1 ma v i2soh i 2 s output high voltage v sup2 - 0.3 vi i2soh = - 1 ma f i2sows i 2 s-word strobe output frequency i2s_ws 48.0 khz f i2socl i 2 s-clock output frequency i2s_cl 1.536 mhz r i2s10/i2s20 i 2 s-clock output high/low-ratio 0.9 1.0 1.1 synchronous i 2 s interface t s_i2s i 2 s input setup time before rising edge of clock i2s_da_in1/2 i2s_cl 12 ns for details see fig. 4C22 i 2 s timing diagram (syn- chronous interface) t h_i2s i 2 s input hold time after rising edge of clock 40 ns t d_i2s i 2 s output delay time after falling edge of clock i2s_cl i2s_ws i2s_da_out 28 ns c l =30 pf f i2sws i 2 s-word strobe input frequency i2s_ws 48.0 khz f i2scl i 2 s-clock input frequency i2s_cl 1.536 mhz r i2scl i 2 s-clock input ratio 0.9 1.1 asynchronous i 2 s interface t s_i2s3 i 2 s3 input setup time before rising edge of clock i2s_cl3 i2s_ws3 i2s_da_in3 4 ns for details see fig. 4C23 i 2 s timing diagram (asyn- chronous interface) t h_i2s3 i 2 s3 input hold time after rising edge of clock 40 ns f i2s3ws i 2 s3-word strobe input frequency i2s_ws3 5 50 khz f i2s3cl i 2 s3-clock input frequency i2s_cl3 3.2 mhz r i2s3cl i 2 s3-clock input ratio 0.9 1.1
preliminary data sheet msp 44x8g micronas 59 fig. 4C22: i 2 s timing diagram (synchronous interface) data: msb first, i 2 s synchronous master r lsb l lsb r lsb l lsb 16/32 bit right channel l lsb l lsb r msb r msb detail c i2s_ws i2s_cl i2s_da_in* ) detail a modus[6] = 1 modus[6] = 0 detail b r lsb r lsb l msb l msb i2s_da_out 16/32 bit right channel 16/32 bit left channel 16/32 bit left channel 1/f i2sws i2s_cl detail c i2s_ws as input i2s_ws as output 1/f i2scl t s_i2s t d_i2s detail a,b i2s_cl i2s_da_out t d_i2s data: msb first, i 2 s synchronous slave r lsb l lsb r lsb l lsb 16, 18...32 bit right channel l lsb l lsb r msb r msb detail c i2s_ws i2s_cl i2s_da_in* ) detail a modus[6] = 1 modus[6] = 0 detail b r lsb r lsb l msb l msb i2s_da_out 16, 18...32 bit right channel 16, 18...32 bit left channel 16,18...32 bit left channel 1/f i2sws t h_i2s t s_i2s i2s_da_in 1) note: 1) i2s_da_in can be - i2s_da_in1, - i2s_da_in2, or - i2s_da_in2/3
msp 44x8g preliminary data sheet 60 micronas fig. 4C23: i 2 s timing diagram (asynchronous interface) 4.6.3.6. analog baseband inputs and outputs, agndc symbol parameter pin name min. typ. max. unit test conditions analog ground v agndc0 agndc open circuit voltage 8-v operation: 5-v operation: agndc 3.77 2.49 v v r load 3 10 m w r outagn agndc output resistance 8-v operation: 5-v operation: 70 47 125 83 180 120 k w k w 3 v v agndc 4 v analog input resistance r insc scart input resistance from t a = 0 to 70 c scn_in_s 1) 25 40 58 k w f signal = 1 khz, i = 0.05 ma r inmono mono input resistance from t a = 0 to 70 c mono_in 152435k w f signal = 1 khz, i = 0.1 ma 1) n means 1, 2, 3, or 4; s means l or r right aligned (i 2 s_config[11] = 1, i 2 s_config[9] = 0) 16 bit data & 16...32 clocks allowed i2s_ws3 i2s_cl3 i2s_da_in3 msb 1/f i2s3ws 1/f i2s3cl i2s_cl3 i2s_da_in3 i2s_ws3 t h_i2s3 right sample (i 2 s_config[10] = 0) right sample (i 2 s_config[10] = 1) left sample (i 2 s_config[10] = 0) left sample (i 2 s_config[10] = 1) msb lsb msb msb lsb i2s_da_in3 i2s_da_in3 left aligned (i 2 s_config[9] = 0) left aligned (i 2 s_config[9] = 1) 16,18...32 bit data & clocks allowed 16,18...32 bit data & clocks allowed t s_i2s3 t s_i2s3
preliminary data sheet msp 44x8g micronas 61 audio analog-to-digital-converter v aicl effective analog input clipping level for analog-to-digital- conversion (8-v operation) scn_in_s, 1) mono_in 2.00 2.25 v rms f signal = 1 khz effective analog input clipping level for analog-to-digital- conversion (5-v operation) 1.13 1.51 v rms scart outputs r outsc scart output resistance at t j = 27 c from t a = 0 to 70 c scn_out_s 1) 200 200 330 460 500 w w f signal = 1 khz, i = 0.1 ma dv outsc deviation of dc-level at scart output from agndc voltage - 70 + 70 mv a sctosc gain from analog input to scart output scn_in_s, 1) mono_in ? scn_out_s 1) - 1.0 + 0.5 db f signal = 1 khz f rsctosc frequency response from analog input to scart output (0 to 20000 hz) - 0.5 + 0.5 db with resp. to 1 khz v outsc effective signal level at scart-output during full-scale digital input signal from i 2 s (8-v operation) scn_out_s 1) 1.8 1.9 2.0 v rms f signal = 1 khz effective signal level at scart-output during full-scale digital input signal from i 2 s (5-v operation) 1.17 1.27 1.37 v rms main and aux outputs r outma main/aux output resistance at t j = 27 c from t a = 0 to 70 c dacp_s 1) 2.1 2.1 3.3 4.6 5.0 k w k w f signal = 1 khz, i = 0.1 ma v outdcma dc-level at main/aux-output for analog volume at 0 db for analog volume at - 30 db (8-v operation) 1.80 2.04 61 2.28 v mv dc-level at main/aux-output for analog volume at 0 db for analog volume at - 30 db (5-v operation) 1.12 1.36 40 1.60 v mv v outma effective signal level at main/ aux-output during full-scale digital input signal from i 2 s for analog volume at 0 db (8-v operation) 1.23 1.37 1.51 v rms f signal = 1 khz effective signal level at main/ aux-output during full-scale digital input signal from i 2 s for analog volume at 0 db (5-v operation) 0.76 0.90 1.04 v rms 1) n means 1, 2, 3, or 4; s means l or r; p means m or a symbol parameter pin name min. typ. max. unit test conditions
msp 44x8g preliminary data sheet 62 micronas 4.6.3.7. sound if inputs 4.6.3.8. power supply rejection symbol parameter pin name min. typ. max. unit test conditions r ifin input impedance ana_in1 + ana_in2 + ana_in - 1.5 6.8 2 9.1 2.5 11.4 k w k w gain agc = 20 db gain agc = 3 db dc vreftop dc voltage at vreftop 2.45 2.65 2.75 v dc ana_in dc voltage on if inputs 1.3 1.5 1.7 v xtalk if crosstalk attenuation 40 db f signal = 1 mhz input level = - 2 dbr bw if 3 db bandwidth 10 mhz agc agc step width 0.85 db symbol parameter pin name min. typ. max. unit test conditions psrr: rejection of noise on ahvsup at 1 khz psrr agndc agndc 80 db from analog input to i 2 s output mono_in, scn_in_s 1) 70 db from analog input to scart output mono_in, scn_in_s 1) scn_out_s 1) 70 db from i 2 s input to scart output scn_out_s 1) 60 db from i 2 s input to main/aux output dacp_s 1) 80 db 1) n means 1, 2, 3, or 4; s means l or r; p means m or a
preliminary data sheet msp 44x8g micronas 63 4.6.3.9. analog performance symbol parameter pin name min. typ. max. unit test conditions specifications for 8-v operation snr signal-to-noise ratio from analog input to i 2 s output mono_in, scn_in_s 1) 90 93 db input level = - 20 db with resp. to v aicl , f sig = 1 khz, a-weighted 20 hz...20 khz from analog input to scart output mono_in, scn_in_s 1) ? scn_out_s 1) 93 96 db input level = - 20 db, f sig = 1 khz, a-weighted 20 hz...20 khz volume = 0 db from i 2 s input to scart output scn_out_s 1) 90 93 db from i 2 s input to main/aux-output dacp_s 1) 90 93 db thd total harmonic distortion from analog input to i 2 s output mono_in, scn_in_s 1) 0.01 0.03 % input level = - 3 dbr with resp. to v aicl , f sig = 1 khz, unweighted 20 hz...20 khz from analog input to scart output mono_in, scn_in_s ? scn_out_s 1) 0.01 0.03 % input level = - 3 dbr, f sig = 1 khz, unweighted 20 hz...20 khz from i 2 s input to scart output scn_out_s 1) 0.01 0.03 % from i 2 s input to main or aux out- put daca_s, dacm_s 1) 0.01 0.03 % 1) n means 1, 2, 3, or 4; s means l or r; p means m or a
msp 44x8g preliminary data sheet 64 micronas specifications for 5-v operation snr signal-to-noise ratio from analog input to i 2 s output mono_in, scn_in_s 1) 87 90 db input level = - 20 db with resp. to v aicl , f sig = 1 khz, a-weighted 20 hz...20 khz from analog input to scart output mono_in, scn_in_s 1) ? scn_out_s 1) 90 93 db input level = - 20 db, f sig = 1 khz, a-weighted 20 hz...20 khz volume = 0 db from i 2 s input to scart output scn_out_s 1) 87 90 db from i 2 s input to main/aux-output for analog volume at 0 db for analog volume at - 30 db dacp_s 1) 87 75 90 80 db db thd total harmonic distortion from analog input to i 2 s output mono_in, scn_in_s 1) 0.03 0.1 % input level = - 3 dbr with resp. to v aicl , f sig = 1 khz, unweighted 20 hz...20 khz from analog input to scart output mono_in, scn_in_s ? scn_out_s 1) 0.1 % input level = - 3 dbr, f sig = 1 khz, unweighted 20 hz...20 khz from i 2 s input to scart output scn_out_s 1) 0.1 % from i 2 s input to main or aux out- put daca_s, dacm_s 1) 0.1 % 1) n means 1, 2, 3, or 4; s means l or r; p means m or a symbol parameter pin name min. typ. max. unit test conditions
preliminary data sheet msp 44x8g micronas 65 crosstalk specifications for 8-v and 5-v operation xtalk crosstalk attenuation input level = - 3 db, f sig = 1 khz, unused analog inputs connected to ground by z < 1 k w between left and right channel within scart input/output pair (l ? r, r ? l) scn_in ? scn_out 1) sc1_in or sc2_in ? i 2 s output sc3_in ? i 2 s output i 2 s input ? scn_out 1) 80 80 80 80 db db db db unweighted 20 hz...20 khz between left and right channel within main or aux output pair i 2 s input ? dacp 1) 75 db unweighted 20 hz...20 khz between scart input/output pairs 1) d = disturbing program o = observed program d: mono/scn_in ? scn_out o: mono/scn_in ? scn_out 1) d: mono/scn_in ? scn_out or unsel. o: mono/scn_in ? i 2 s output d: mono/scn_in ? scn_out o: i 2 s input ? scn_out 1) d: mono/scn_in ? unselected o: i 2 s input ? sc1_out 1) 100 95 100 100 db db db db (unweighted 20 hz...20 khz) same signal source on left and right disturbing chan- nel, effect on each observed output channel crosstalk between main and aux output pairs i 2 s input dsp ? dacp 1) 90 db (unweighted 20 hz...20 khz) same signal source on left and right disturbing chan- nel, effect on each observed output channel xtalk crosstalk from main or aux output to scart output and vice versa d = disturbing program o = observed program d: mono/scn_in/dsp ? scn_out o: i 2 s input ? dacp 1) d: mono/scn_in/dsp ? scn_out o: i 2 s input ? dacp 1) d: i 2 s input ? dacp o: mono/scn_in ? scn_out 1) d: i 2 s input ? dacm o: i 2 s input ? scn_out 1) 80 85 95 95 db db db db (unweighted 20 hz...20 khz) same signal source on left and right disturbing chan- nel, effect on each observed output channel scart output load resis- tance 10 k w scart output load resis- tance 30 k w 1) n means 1, 2, 3, or 4; s means l or r; p means m or a symbol parameter pin name min. typ. max. unit test conditions
msp 44x8g preliminary data sheet 66 micronas 4.6.3.10. sound standard dependent characteristics symbol parameter pin name min. typ. max. unit test conditions nicam characteristics (msp standard code = 8) dv nicamout tolerance of output voltage of nicam baseband signal dacp_s scn_out_s 1) - 1.5 + 1.5 db 2.12 khz, modulator input level = 0 dbref s/n nicam s/n of nicam baseband signal 72 db nicam: - 6 db, 1 khz, rms unweighted 0 to 15 khz, vol = 9 db nic_presc = 7fh output level 1 v rms at dacp_s thd nicam total harmonic distortion + noise of nicam baseband signal 0.1 % 2.12 khz, modulator input level = 0 dbref ber nicam nicam: bit error rate 1 10 - 7 fm + nicam, norm conditions fr nicam nicam frequency response, 20...15000 hz - 1.0 + 1.0 db modulator input level = - 12 db dbref; rms xtalk nicam nicam crosstalk attenuation (dual) 80 db sep nicam nicam channel separation (stereo) 80 db fm characteristics (msp standard code = 3) dv fmout tolerance of output voltage of fm demodulated signal dacp_s, scn_out_s 1) - 1.5 + 1.5 db 1 fm-carrier, 50 m s, 1 khz, 40 khz deviation; rms s/n fm s/n of fm demodulated signal 73 db 1 fm-carrier 5.5 mhz, 50 m s, 1 khz, 40 khz devi- ation; rms, unweighted 0 to 15 khz (for s/n); full input range, fm-pres- cale = 46 h, vol = 0 db ? output level 1 v rms at dacp_s thd fm total harmonic distortion + noise of fm demodulated signal 0.1 % fr fm fm frequency responses, 20...15000 hz - 1.0 + 1.0 db 1 fm-carrier 5.5 mhz, 50 m s, modulator input level = - 14.6 dbref; rms xtalk fm fm crosstalk attenuation (dual) 80 db 2 fm-carriers 5.5/5.74 mhz, 50 m s, 1 khz, 40 khz deviation; bandpass 1 khz sep fm fm channel separation (stereo) 50 db 2 fm-carriers 5.5/5.74 mhz, 50 m s, 1 khz, 40 khz deviation; rms 1) n means 1, 2, 3, or 4; s means l or r; p means m or a 2) eim refers to 75- m s equivalent input modulation. it is defined as the audio-signal level which results in a stated percentage modulation, when the dbx encoding process is replaced by a 75- m s preemphasis network.
preliminary data sheet msp 44x8g micronas 67 am characteristics (msp standard code = 9) s/n am(1) s/n of am demodulated signal measurement condition: rms/flat dacp_s, scn_out_s 1) 55 db sif level: 0.1 - 0.8 v pp am-carrier 54% at 6.5 mhz vol = 0 db, fm/am prescaler set for output = 0.5 v rms at main out; standard code = 09 hex no video/chrominance components s/n am(2) s/n of am demodulated signal measurement condition: qp/ccir 45 db thd am total harmonic distortion + noise of am demodulated signal 0.6 % fr am am frequency response 50 hz... 12 khz - 2.5 + 1.0 db btsc characteristics (msp standard code = 20 hex , 21 hex ) s/n btsc s/n of btsc stereo signal s/n of btsc-sap signal dacp_s, scn_out_s 1) 68 57 db db 1 khz l or r or sap, 100% modulation, 75 m s deem- phasis, rms unweighted 0 to 15 khz thd btsc thd + n of btsc stereo signal thd + n of btsc sap signal 0.1 0.5 % % 1 khz l or r or sap, 100% 75 m s eim 2) , dbx nr, rms unweighted 0 to 15 khz fr btsc frequency response of btsc stereo, 50 hz...12 khz frequency response of btsc sap, 50 hz...9 khz - 0.5 - 1.0 0.5 0.6 db db l or r or sap, 1%...66% eim 2) , dbx nr xtalk btsc stereo ? sap sap ? stereo 76 80 db db 1 khz l or r or sap, 100% modulation, 75 m s deem- phasis, bandpass 1 khz sep btsc stereo separation 50 hz...10 khz 50 hz...12 khz 35 30 db db l or r 1%...66% eim 2) , dbx nr fm thrpilot pilot deviation threshold stereo off ? on stereo on ? off ana_in1+, ana_in2+ 3.2 1.2 3.5 1.5 khz khz 4.5 mhz carrier modulated with f h =15.743 khz sif level=100mv pp indication: status bit[6] f pilot pilot frequency range ana_in1+ ana_in2+ 15.563 15.843 khz standard btsc stereo sig- nal, sound carrier only symbol parameter pin name min. typ. max. unit test conditions 1) n means 1, 2, 3, or 4; s means l or r; p means m or a 2) eim refers to 75- m s equivalent input modulation. it is defined as the audio-signal level which results in a stated percentage modulation, when the dbx encoding process is replaced by a 75- m s preemphasis network.
msp 44x8g preliminary data sheet 68 micronas btsc characteristics (msp standard code = 20 hex , 21 hex ) with a minimum if input signal level of 70 mvpp (measured without any video/chroma signal components) s/n btsc s/n of btsc stereo signal s/n of btsc-sap signal dacp_s, scn_out_s 1) 64 55 db db 1 khz l or r or sap, 100% modulation, 75 m s deem- phasis, rms unweighted 0 to 15 khz thd btsc thd + n of btsc stereo signal thd + n of btsc sap signal 0.15 0.8 % % 1 khz l or r or sap, 100% 75 m s eim 2) , dbx nr, rms unweighted 0 to 15 khz fr btsc frequency response of btsc ste- reo, 50 hz...12 khz frequency response of btsc- sap, 50 hz...9 khz - 0.5 - 1.0 0.5 0.6 db db l or r or sap, 1%...66% eim 2) , dbx nr xtalk btsc stereo ? sap sap ? stereo 75 75 db db 1 khz l or r or sap, 100% modulation, 75 m s deem- phasis, bandpass 1 khz sep btsc stereo separation 50 hz...10 khz 50 hz...12 khz 35 30 db db l or r 1%...66% eim 2) , dbx nr eia-j characteristics (msp standard code = 30 hex ) s/n eiaj s/n of eia-j stereo signal s/n of eiaj sub-channel dacp_s, scn_out_s 1) 60 60 db db 1 khz l or r, 100% modulation, 75 m s deemphasis, rms unweighted 0 to 15 khz thd eiaj thd + n of eia-j stereo signal thd + n of eia-j sub-channel 0.2 0.3 % % fr eiaj frequency response of eia-j stereo, 50 hz...12 khz frequency response of eia-j sub- channel, 50 hz...12 khz - 0.5 - 1.0 0.5 0.5 db db 100% modulation, 75 m s deemphasis xtalk eiaj main ? sub sub ? main 66 80 db db 1 khz l or r, 100% modu- lation, 75 m s deemphasis, bandpass 1 khz sep eiaj stereo separation 50 hz...5 khz 50 hz...10 khz 35 28 db db eia-j stereo signal, l or r 100% modulation fm-radio characteristics (msp standard code = 40 hex ) s/n ukw s/n of fm-radio stereo signal dacp_s, scn_out_s 1) 70 db 1 khz l or r, 100% modu- lation, 75 m s deemphasis, rms unweighted 0 to 15 khz thd ukw thd + n of fm-radio stereo signal 0.1 % fr ukw frequency response of fm-radio stereo 50 hz...15 khz - 1.0 0.5 db l or r, 1%...100% modula- tion, 75 m s deemphasis sep ukw stereo separation 50 hz...15 khz 45 db f pilot pilot frequency range ana_in1+ ana_in2+ 18.844 19.125 khz standard fm radio stereo signal symbol parameter pin name min. typ. max. unit test conditions 1) n means 1, 2, 3, or 4; s means l or r; p means m or a 2) eim refers to 75- m s equivalent input modulation. it is defined as the audio-signal level which results in a stated percentage modulation, when the dbx encoding process is replaced by a 75- m s preemphasis network.
preliminary data sheet msp 44x8g micronas 69 5. appendix a: overview of tv-sound standards 5.1. nicam 728 table 5C1: summary of nicam 728 sound modulation parameters specification i b/g l d/k carrier frequency of digital sound 6.552 mhz 5.85 mhz 5.85 mhz 5.85 mhz transmission rate 728 kbit/s type of modulation differentially encoded quadrature phase shift keying (dqpsk) spectrum shaping roll-off factor by means of roll-off filters 1.0 0.4 0.4 0.4 carrier frequency of analog sound component 6.0 mhz fm mono 5.5 mhz fm mono 6.5 mhz am mono 6.5 mhz fm mono terrestrial cable power ratio between vision carrier and analog sound carrier 10 db 13 db 10 db 16 db 13 db power ratio between analog and modulated digital sound carrier 10 db 7 db 17 db 11 db china/ hungary poland 12 db 7 db table 5C2: summary of nicam 728 sound coding characteristics characteristics values audio sampling frequency 32 khz number of channels 2 initial resolution 14 bit/sample companding characteristics near instantaneous, with compression to 10 bits/sample in 32-samples (1 ms) blocks coding for compressed samples 2s complement preemphasis ccitt recommendation j.17 (6.5 db attenuation at 800 hz) audio overload level + 12 dbm measured at the unity gain frequency of the preemphasis network (2 khz)
msp 44x8g preliminary data sheet 70 micronas 5.2. a2-systems table 5C3: key parameters for a2 systems of standards b/g, d/k, and m characteristics sound carrier fm1 sound carrier fm2 tv-sound standard b/g d/k m b/g d/k m carrier frequency in mhz 5.5 6.5 4.5 5.7421875 6.2578125 6.7421875 4.724212 vision/sound power difference 13 db 20 db sound bandwidth 40 hz to 15 khz preemphasis 50 m s75 m s50 m s75 m s frequency deviation (nom/max) 27 / 50 khz 17 / 25 khz 27 / 50 khz 15 / 25 khz transmission modes mono transmission mono mono stereo transmission (l + r)/2 (l + r)/2 r (l - r)/2 dual sound transmission language a language b identification of transmission mode pilot carrier frequency 54.6875 khz 55.0699 khz max. deviation portion 2.5 khz type of modulation / modulation depth am / 50% modulation frequency mono: unmodulated stereo: 117.5 hz dual: 274.1 hz 149.9 hz 276.0 hz
preliminary data sheet msp 44x8g micronas 71 5.3. btsc-sound system 5.4. japanese fm stereo system (eia-j) table 5C4: key parameters for btsc-sound systems aural carrier btsc-mpx-components (l + r) pilot (l - r) sap prof. ch. carrier frequency (f h = 15.734 khz) 4.5 mhz baseband f h 2 f h 5 f h 6.5 f h sound bandwidth in khz 0.05 - 15 0.05 - 15 0.05 - 12 0.05 - 3.4 preemphasis 75 m s dbx dbx 150 m s max. deviation to aural carrier 73 khz (total) 25 khz 1) 5khz 50khz 1) 15 khz 3 khz max. freq. deviation of subcarrier modulation type am 10 khz fm 3khz fm 1) sum does not exceed 50 khz due to interleaving effects table 5C5: key parameters for japanese fm-stereo sound system eia-j aural carrier fm eia-j-mpx-components (l + r) (l - r) identification carrier frequency (f h = 15.734 khz) 4.5 mhz baseband 2 f h 3.5 f h sound bandwidth 0.05 - 15 khz 0.05 - 15 khz - preemphasis 75 m s75 m s none max. deviation portion to aural carrier 47 khz 25 khz 20 khz 2 khz max. freq. deviation of subcarrier modulation type 10 khz fm 60% am transmitter-sided delay 20 m s0 m s0 m s mono transmission l + r - unmodulated stereo transmission l + rl - r 982.5 hz bilingual transmission language a language b 922.5 hz
msp 44x8g preliminary data sheet 72 micronas 5.5. fm satellite sound 5.6. fm-stereo radio table 5C6: key parameters for fm satellite sound carrier frequency maximum fm deviation sound mode bandwidth deemphasis 6.5 mhz 85 khz mono 15 khz 50 m s 7.02/7.20 mhz 50 khz mono/stereo/bilingual 15 khz adaptive 7.38/7.56 mhz 50 khz mono/stereo/bilingual 15 khz adaptive 7.74/7.92 mhz 50 khz mono/stereo/bilingual 15 khz adaptive table 5C7: key parameters for fm-stereo radio systems aural carrier fm-radio-mpx-components (l + r) pilot (l - r) rds/ari carrier frequency (f p = 19 khz) 10.7 mhz baseband f p 2 f p 3 f p sound bandwidth in khz 0.05 - 15 0.05 - 15 preemphasis: - usa - europe 75 m s 50 m s 75 m s 50 m s max. deviation to aural carrier 75 khz (100%) 90% 1) 10% 90% 1) 5% 1) sum does not exceed 90% due to interleaving effects
preliminary data sheet msp 44x8g micronas 73 6. appendix b: manual mode to adapt the modes of the standard select regis- ter to individual requirements, the msp 44x8g offers a manual mode, which provides sophisticated program- ming of the msp 44x8g. the manual mode can be used only in those cases, where user specific requirements concerning detec- tion, identification, or carrier positioning have to be met. after the setting of the standard select register, the msp 44x8g is set up for optimal behavior. there- fore, it is not recommended to use the manual mode. 6.1. demodulator write and read registers for manual mode in case of automatic sound select (modus[0]=1), any modifications of all dco registers listed in table 6C1 are ignored. table 6C1: demodulator write registers; subaddress: 10 hex ; these registers are not readable! demodulator write registers address (hex) msp- version description reset mode page auto_fm/am 00 21 4418, 4458 1) 1. modus[0]=1 (automatic sound select): switching level threshold of automatic switching between nicam and fm/am in case of bad nicam reception 2. modus[0]=0 (manual mode): activation and configuration of automatic switching between nicam and fm/am in case of bad nicam reception 00 00 hex 74 a2_threshold 00 22 a2 stereo identification threshold 00 19 hex cm_threshold 00 24 carrier-mute threshold 00 2a hex dco1_lo dco1_hi dco2_lo dco2_hi 00 93 00 9b 00 a3 00 ab note: modifications are ignored for automatic sound select = on (modus[0]=1) increment channel 1 low part increment channel 1 high part increment channel 2 low part increment channel 2 high part 00 00 hex 77 1) not in btsc, eia-j, and fm-radio mode table 6C2: demodulator read registers; subaddress: 11 hex ; these registers are not writable! demodulator read registers address (hex) msp- version description page c_ad_bits 00 23 4410, 4450 nicam-sync bit, nicam-c-bits, and bit[2:0] of additional data bits 78 add_bits 00 38 nicam: bit[10:3] of additional data bits 78 cib_bits 00 3e nicam: cib1 and cib2 control bits 78 error_rate 00 57 nicam error rate, updated with 182 ms 78
msp 44x8g preliminary data sheet 74 micronas 6.2. dsp write and read registers for manual mode 6.3. manual mode: description of demodulator write registers 6.3.1. automatic switching between nicam and analog sound in case of bad nicam reception or loss of the nicam-carrier, the msp 44x8g offers an automatic switching (fall back) to the analog sound (fm/am- mono), without the necessity of the controller reading and evaluating any parameters. if a proper nicam sig- nal returns, switching back to this source is performed automatically as well. the feature evaluates the nicam error_rate and switches, if necessary, all output channels which are assigned to the nicam source, to the analog source, and vice versa. an appropriate hysteresis algorithm avoids oscillating effects (see fig. 6C1). status[9] and c_ad_bits[11] (addr: 0023 hex ) provide information about the actual nicam-fm/am-status. fig. 6C1: hysteresis for automatic switching 6.3.1.1. function in automatic sound select mode the automatic sound select feature (modus[0]=1) includes the procedure mentioned above. by default, the internal error_rate threshold is set to 700 dec . i.e.: Cnicam ? analog sound if error_rate > 700 C analog sound ? nicam if error_rate < 700/2 table 6C3: dsp-write registers; subaddress: 12 hex , all registers are readable as well write register address (hex) bits operational modes and adjustable range reset mode page additional channel matrix modes 00 08 00 09 00 0a 00 41 00 0b 00 0c [7:0] [sum/diff, ab_xchange, phase_change_b, phase_change_a, a_only, b_only] 00 hex 79 fm fixed deemphasis 00 0f [15:8] [off, 50 m s, 75 m s] off 79 fm adaptive deemphasis [7:0] [off, wp1] off 79 identification mode 00 15 [7:0] [b/g, m] b/g 79 table 6C4: dsp read registers; subaddress: 13 hex , all registers are not writable additional read registers address (hex) bits output range page stereo detection register for a2 stereo systems 00 18 [15:8] [80 hex ... 7f hex ] 8 bit twos complement 80 dc level readout fm1/ch2-l 00 1b [15:0] [8000 hex ... 7fff hex ] 16 bit twos complement 80 dc level readout fm2/ch1-r 00 1c [15:0] [8000 hex ... 7fff hex ] 16 bit twos complement 80 error_rate selected sound nicam analog sound threshold threshold/2
preliminary data sheet msp 44x8g micronas 75 the error_rate value of 700 corresponds to a ber of approximately 5.46*10 -3 /s. individual configuration of the threshold can be done using table 6C5, whereby the bits [0] and [11] of auto_fm are ignored. it is recommended to use the internal setting used by the standard selection. the optimum nicam sound can be assigned to the msp output channels by selecting one of the stereo or a/b, stereo or a, or stereo or b source channels. 6.3.1.2. function in manual mode if the manual mode (modus[0]=0) is required, the activation and configuration of the automatic switching feature has to be done as described in table 6C5. note, that the channel matrix of the corresponding out- put channels must be set according to the nicam mode and need not to be changed in the fm/am-fallback case. example: required threshold = 500: bits [10:1]=00 1111 1010 table 6C5: coding of automatic nicam/analog sound switching; reset status: mode 0; automatic sound select is on (modus[0] = 1 ) mode description auto_fm [11:0] addr. = 00 21 hex error_rate- threshold/dec source select: input at nicam path 1) 1 automatic switching with internal threshold (default, if automatic sound select is on) bit[11] = ignored bit[10:1] = 0 bit[0] = ignored 700 nicam or fm/am, depending on error_rate 2 automatic switching with external threshold (customizing of automatic sound select) bit[11] = ignored bit[10:1] = 25...1000 = threshold/2 bit[0] = ignored set by customer; recommended range: 50...2000 1) the nicam path may be assigned to stereo or a/b, stereo or a, or stereo or b source channels (see table 2C2 on page 11). table 6C6: coding of automatic nicam/analog sound switching; reset status: mode 0; automatic sound select is off (modus[0] = 0 ) mode description auto_fm [11:0] addr. = 00 21 hex error_rate- threshold/dec source select: input at nicam path 0 forced nicam (automatic switching disabled) bit[11] = 0 bit[10:1] = 0 bit[0] = 0 none always nicam; mute in case of no nicam available 1 automatic switching with internal threshold (default, if automatic sound select is on) bit[11] = 0 bit[10:1] = 0 bit[0] = 1 700 nicam or fm/am, depending on error_rate 2 automatic switching with external threshold (customizing of automatic sound select) bit[11] = 0 bit[10:1] = 25...1000 = threshold/2 bit[0] = 1 set by customer; recommended range: 50...2000 3 forced analog mono (automatic switching disabled) bit[11] = 1 bit[10:1] = 0 bit[0] = 1 none always fm/am
msp 44x8g preliminary data sheet 76 micronas 6.3.2. a2 threshold the threshold between stereo/bilingual and mono identification for the a2 standard has been made pro- grammable according to the users preferences. an internal hysteresis ensures robustness and stability. 6.3.3. carrier-mute threshold the carrier-mute threshold has been made program- mable according to the users preferences. an internal hysteresis ensures stable behavior. table 6C7: write register on i 2 c subaddress 10 hex : a2 threshold register address function name thresholds 00 22 hex (write) a2 threshold register defines threshold of all a2 and eia_j standards for stereo and bilingual detection bit[11:0] 7f0 hex force mono identification ... 190 hex default setting after reset ... 0a0 hex minimum threshold for stable detection recommended range: 0a hex ...3c hex a2_thresh table 6C8: write register on i 2 c subaddress 10 hex : carrier-mute threshold register address function name thresholds 00 24 hex (write) carrier-mute threshold register defines threshold for the carrier mute feature bit[6:0] 00 hex carrier-mute always on (both channels muted) ... 2a hex default setting after reset ... ff hex carrier-mute always off (both channels forced on) recommended range: 14 hex ...50 hex cm_thresh
preliminary data sheet msp 44x8g micronas 77 6.3.4. dco-registers note: the use of this register is not recommended. it should be used only in cases where non-standard car- rier frequencies have to be processed. please note, that the usage of user specific demodulation frequen- cies is not possible in combination with the automatic sound select (modus[0]=1). when selecting a tv-sound standard by means of the standard select register, all frequency tuning is performed automatically. if manual setting of the tuning frequency is required, a set of 24-bit registers determining the mixing frequen- cies of the quadrature mixers can be written manually into the msp. in table 6C9, examples for dco register programming are listed. it is necessary to separate these registers into two categories: low part and high part. the formula for the calculation of the incr val- ues for any chosen if frequency is as follows: incr dec = int (f / fs 2 24 ) with: int = integer function f = if frequency in mhz f s = sampling frequency (18.432 mhz) conversion of incr into hex-format and separation of the 12-bit low and high parts lead to the required regis- ter values (dco1_hi and _lo for msp-ch1, dco2_hi and _lo for msp-ch2). 6.4. manual mode: description of demodulator read registers note: this register should be used only in cases where software compatibility to the msp 44x0d is required. using the standard selection register together with the status register provides a more economic way to program the msp 44x8g and to retrieve information from the msp. all registers except c_ad_bits are 8 bits wide. they can be read out of the ram of the msp 44x8g. all transmissions take place in 16-bit words. the valid 8-bit data are the 8 lsbs of the received data word. if the automatic sound select feature is not used, the nicam or fm-identification parameters must be read and evaluated by the controller in order to enable appropriate switching of the channel select matrix of the baseband processing part. the fm-identification registers are described in section 6.6.1. to handle the nicam-sound and to observe the nicam-quality, at least the registers c_ad_bits and error_rate must be read and evaluated by the controller. addi- tional data bits and cib bits, if supplied by the nicam transmitter, can be obtained by reading the registers add_bits and cib_bits. table 6C9: dco registers for the msp 44x8g ; reset status: dco_hi/lo = 00 00 dco1_lo 00 93 hex , dco1_hi 00 9b hex ; dco2_lo 00 a3 hex , dco2_hi 00 ab hex if-freq. [mhz] dco_hi [hex] dco_lo [hex] if-freq. [mhz] dco_hi [hex] dco_lo [hex] 4.5 03e8 0000 5.04 5.5 5.58 5.7421875 04 60 04 c6 04 d8 04 fc 00 00 03 8e 00 00 00 aa 5.76 5.85 5.94 05 00 05 14 05 28 00 00 00 00 00 00 6.0 6.2 6.5 6.552 05 35 05 61 05 a4 05 b0 05 55 0c 71 07 1c 00 00 6.6 6.65 6.8 05 ba 05 c5 05 e7 0a aa 0c 71 01 c7 7.02 06 18 00 00 7.2 06 40 00 00 7.38 06 68 00 00 7.56 06 90 00 00
msp 44x8g preliminary data sheet 78 micronas 6.4.1. nicam mode control/additional data bits register nicam operation mode control bits and a[2:0] of the additional data bits. format: important: s = bit[0] indicates correct nicam-syn- chronization (s = 1). if s = 0, the msp 4418/4458g has not yet synchronized correctly to frame and sequence, or has lost synchronization. the remaining read registers are therefore not valid. the msp mutes the nicam output automatically and tries to synchro- nize again as long as any nicam standard is selected by the standard select register. the operation mode is coded by c4-c1 as shown in table 6C10. note: it is not necessary to read out and evaluate the c_ad_bits. all evaluation is performed in the msp and indicated in the status register. 6.4.2. additional data bits register contains the remaining 8 of the 11 additional data bits. the additional data bits are not yet defined by the nicam 728 system. format: 6.4.3. cib bits register cib bits 1 and 2 (see nicam 728 specifications). format: 6.4.4. nicam error rate register average error rate of the nicam reception in a time interval of 182 ms, which should be close to 0. the ini- tial and maximum value of error_rate is 2047. this value is also active if no nicam-standard is selected. since the value is achieved by filtering, a cer- tain transition time (approx. 0.5 sec) is unavoidable. acceptable audio may have error rates up to a value of 700 dec . individual evaluation of this value by the con- troller and an appropriate threshold may define the fall- back mode from nicam to fm/am-mono in case of poor nicam reception. the bit error rate per second (ber) can be calculated by means of the following formula: ber = error_rate * 12.3*10 - 6 /s msb c_ad_bits 00 23 hex lsb 11...76543210 auto _fm ... a[2] a[1] a[0] c4 c3 c2 c1 s table 6C10: nicam operation modes as defined by the ebu nicam 728 specification c4 c3 c2 c1 operation mode 0 0 0 0 stereo sound (nicama/b), independent mono sound (fm1) 0 0 0 1 two independent mono signals (nicama, fm1) 0 0 1 0 three independent mono channels (nicama, nicamb, fm1) 0 0 1 1 data transmission only; no audio 1 0 0 0 stereo sound (nicama/b), fm1 carries same channel 1 0 0 1 one mono signal (nicama). fm1 carries same channel as nicama 1 0 1 0 two independent mono channels (nicama, nicamb). fm1 carries same channel as nicama 1 0 1 1 data transmission only; no audio x 1 x x unimplemented sound coding option (not yet defined by ebu nicam 728 specification) auto_fm: monitor bit for the auto_fm status: 0: nicam source is nicam 1: nicam source is fm msb add_bits 00 38 hex lsb 76543210 a[10] a[9] a[8] a[7] a[6] a[5] a[4] a[3] msb cib_bits 00 3e hex lsb 76543210 xxxxxxcib1cib2 error_rate 00 57 hex error free 0000 hex maximum error rate 07ff hex
preliminary data sheet msp 44x8g micronas 79 6.5. manual mode: description of dsp write registers 6.5.1. additional channel matrix modes this table shows additional modes for the channel matrix registers. the sum/difference mode can be used together with the quasi-peak detector to determine the sound mate- rial mode. if the difference signal on channel b (right) is near to zero, and the sum signal on channel a (left) is high, the incoming audio signal is mono. if there is a significant level on the difference signal, the incoming audio is stereo. 6.5.2. fm fixed deemphasis 6.5.3. fm adaptive deemphasis note: the adaptive deemphasis wp1 requires setting of fixed deemphasis to 75 m s. 6.5.4. nicam deemphasis a j17 deemphasis is always applied to the nicam sig- nal. it is not switchable. 6.5.5. identification mode for a2 stereo systems to shorten the response time of the identification algo- rithm after a program change between two fm-stereo capable programs, the reset of the ident-filter can be applied. sequence: 1. program change 2. reset ident-filter 3. set identification mode back to standard b/g or m 4. read stereo detection register main matrix 00 08 hex l aux matrix 00 09 hex l scart1 matrix 00 0a hex l scart2 matrix 00 41 hex l i 2 s matrix 00 0b hex l quasi-peak detector matrix 00 0c hex l sum/diff 0100 0000 40 hex ab_xchange 0101 0000 50 hex phase_change_b 0110 0000 60 hex phase_change_a 0111 0000 70 hex a_only 1000 0000 80 hex b_only 1001 0000 90 hex fm deemphasis 00 0f hex h 50 m s 0000 0000 00 hex reset 75 m s 0000 0001 01 hex off 0011 1111 3f hex fm adaptive deemphasis wp1 00 0f hex l off 0000 0000 00 hex reset wp1 0011 1111 3f hex identification mode 00 15 hex l standard b/g (german stereo) 0000 0000 00 hex reset standard m (korean stereo) 0000 0001 01 hex reset of ident-filter 0011 1111 3f hex
msp 44x8g preliminary data sheet 80 micronas 6.6. manual mode: description of dsp read registers all readable registers are 16-bit wide. transmissions via i 2 c bus have to take place in 16-bit words. some of the defined 16-bit words are divided into low and high byte, thus holding two different control entities. these registers are not writable. 6.6.1. stereo detection register for a2 stereo systems note: it is not necessary to read out and evaluate the a2 identification level. all evaluation is performed in the msp and indicated in the status register. 6.6.2. dc level register the dc level register measures the dc component of the incoming fm signals (fm1 and fm2). this can be used for seek functions in satellite receivers and for if fm frequencies fine tuning. if the dco frequency is lower than the actuel carrier frequency, the resulting dc level will be positive, an dvia versa. in the audio signal the dc content is suppressed. the time con- stant t, defining the transition time of the dc level register, is approximately 28 ms. 6.7. demodulator source channels in manual mode 6.7.1. terrestrial sound standards table 6C11 shows the source channel assignment of the demodulated signals in case of manual mode for all terrestrial sound standards. see table 2C2 for the assignment in the automatic sound select mode. in manual mode for terrestrial sound standards, only two demodulator sources are defined. 6.7.2. sat sound standards table 6C12 shows the source channel assignment of the demodulated signals for sat sound standards. stereo detection register 00 18 hex h stereo mode reading (twos complement) mono near zero stereo positive value (ideal reception: 7f hex ) bilingual negative value (ideal reception: 80 hex) dc level readout fm1 (msp-ch2) 00 1b hex h + l dc level readout fm2 (msp-ch1) 00 1c hex h + l dc level [8000 hex ... 7fff hex ] values are 16 bit twos complement
preliminary data sheet msp 44x8g micronas 81 table 6C11: manual sound select mode for terrestrial sound standards source channels of sound select block broadcasted sound standard selected msp standard code broadcasted sound mode fm matrix fm/am (use 0 for channel select) stereo or a/b (use 1 for channel select) b/g-fm d/k-fm m-korea m-japan 03 04, 05 02 30 mono sound a mono mono mono stereo german stereo korean stereo stereo stereo bilingual, languages a and b no matrix left = a right = b left = a right = b b/g-nicam l-nicam i-nicam d/k-nicam d/k-nicam (with high deviation fm) 08 09 0a 0b 0c nicam not available or nicam error rate too high sound a mono analog mono no sound with auto_fm: analog mono mono sound a mono analog mono nicam mono stereo sound a mono analog mono nicam stereo bilingual, languages a and b sound a mono analog mono left = nicam a right = nicam b btsc 20 mono sound a mono mono mono stereo korean stereo stereo stereo mono + sap sound a mono mono mono stereo + sap korean stereo stereo stereo 21 mono sound a mono mono mono stereo mono + sap no matrix left = mono right = sap left = mono right = sap stereo + sap fm-radio 40 mono sound a mono mono mono stereo korean stereo stereo stereo table 6C12: manual sound select modes for sat-reception (fm matrix is set automatically) source channels of sound select block for sat-modes broadcasted sound standard selected msp standard code broadcasted sound mode fm/am (source select: 0) stereo or a/b (source select: 1) stereo or a (source select: 3) stereo or b (source select: 4) fm sat 6, 50 hex mono mono mono mono mono 51 hex stereo stereo stereo stereo stereo bilingual left = a (fm1) right = b (fm2) left = a (fm1) right = b (fm2) a (fm1) b (fm2)
msp 44x8g preliminary data sheet 82 micronas 7. appendix c: application information 7.1. exclusions of audio baseband features in general, all functions can be switched independently. two exceptions exist: 1. nicam cannot be processed simultaneously with secondary channel (see fig. 2C3 and fig. 2C2 on page 10). 2. fm adaptive deemphasis cannot be processed simultaneously with fm-identification. 7.2. phase relationship of analog outputs the analog output signals: main, aux, and scart2 all have the same phases. the scart1 output has oppo- site phase. using the i 2 s-outputs for other dsps or d/a convert- ers, care must be taken to adjust for the correct phase. fig. 7C1: phase diagram of the msp 44x8g scart2-ch. scart1 scart1 scart2 scart4 scart3 mono main audio scart dsp input select scart output select baseband processing aux scart1-ch. scart2 i2s_out1/2 i2s_in1/2/3 mono, scart1...4
preliminary data sheet msp 44x8g micronas 83 7.3. application circuit sc1_out_l 37 sc1_out_r 36 sc2_out_l 34 sc2_out_r 33 39 ahvsup 44 ahvss 66 avsup 13 dvsup 16 dvss 21 resetq 62 avss 35 vref1 26 vref2 5 v 5 v 8 v avss 5v 5v capl_m 40 capl_a 38 vreftop 58 agndc 45 ana_in1+ 67 ana_in2+ 69 ana_in - 68 xtal_in 71 xtal_out 72 msp 44x8g d_ctr_i/o_0 78 d_ctr_i/o_1 77 aud_cl_out 74 testen 70 + 100 w 100 w 100 w 100 w 22 m f 22 m f 22 m f 22 m f + + + daca_r 24 1 nf 1 nf 1 nf 1 nf daca_l 25 dacm_r 27 dacm_l 28 1 m f 1 m f 1 m f 1 m f main channel tuner 1 tuner 2 if 2 in signal gnd if 1 in 56 pf 56 pf 56 pf + 3.3 m f 100 nf 100 nf 10 m f + if ana_in2+ 8v(5v) 18.432 mhz + + 10 m f10 m f 60 mono_in 56 sc1_in_l 57 sc1_in_r 55 asg 53 sc2_in_l 54 sc2_in_r 52 asg 50 sc3_in_l 51 sc3_in_r 49 asg 47 sc4_in_l 48 sc4_in_r 80 standbyq 79 adr_sel 3 i2c_da 2 i2c_cl 75 adr_ws 10 adr_cl 8 adr_da 5 i2s_ws 4 i2s_cl 7 i2s_da_in1 17 i2s_da_in2/3 6 i2s_da_out 220 pf alternative circuit for ana_in1+ for more attenuation of video 100 pf 56 pf 1 k w ana_in1+ ahvss ahvss ahvss 330 nf 330 nf 330 nf 330 nf 330 nf 330 nf 330 nf 330 nf 330 nf dvss dvss avss components: c s. section 4.6.2. resetq (from controller, see section 4.6.3.3.) note: pin numbers refer to the pqfp80 package. 1.5 nf 470 pf 10 m f 1.5 nf 470 pf 10 m f 1.5 nf 470 pf 10 m f 22 i2s_da_in3 20 i2s_ws_3 19 i2s_cl_3 aux channel/ fm-modulator aux channel dvss ahvss (5 v) not used ahvss ahvss
all information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. any new issue of this data sheet invalidates previous issues. product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples deliv- ered. by this publication, micronas gmbh does not assume responsibil- ity for patent infringements or other rights of third parties which may result from its use. further, micronas gmbh reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. no part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of micronas gmbh. msp 44x8g preliminary data sheet 84 micronas micronas gmbh hans-bunte-strasse 19 d-79108 freiburg (germany) p.o. box 840 d-79008 freiburg (germany) tel. +49-761-517-0 fax +49-761-517-2174 e-mail: docservice@micronas.com internet: www.micronas.com printed in germany order no. 6251-516-1pd 8. data sheet history 1. preliminary data sheet : msp 44x8g multistandard sound processor family, feb. 25, 2000, 6251-516-1pd. first release of the preliminary data sheet.
micronas page 1 of 1 subject: data sheet concerned: supplement: edition: preliminary data sheet supplement version changes within the msp 34xxg family: for a detailed description of the below-mentioned items, see the corresponding data sheets. for quick reference, check the version history in the data sheet appendices. msp 34x0g a4 b4 b5 b6 b8 msp 34x1g a1 a2 b8 msp 34x2g a1 msp 34x5g a4 b5 b6 b8 msp 34x7g b6 b8 technology 0.8 0.5 0.5 0.5 0.45 power dissipation (typical) at 8 v operation msp 34x0/x1/x5/x7 msp 34x2 740 mw 640 mw 640 mw 640 mw 690 mw 600 mw digital input specification change x x x specification of max. analog high voltage (ahvsup) 8.4 v 8.4 v 8.7 v 8.7 v 8.7 v programmable a2 and carrier mute thresholds x x x new standard select mode 0d hex : d/k-nicam together with hdev3 fm mode x x x additional preference color for 4.5 mhz carrier in automatic standard detection x x x improved am-performance (better snr and thd) x x new standard select mode 07 hex : d/k3 for poland x x faster system d/k loop for stereo detection (standards 4, 5, 7, b with ass = on) x x improved i 2 c hardware problem handling x x extended features in the control register (readout hardware / reset status) x x micronas dynamic bass (mdb) msp 34x0/x1/x2 x x micronas dynamic bass (improved mdb) msp 34x0/x1/x2 x faster identification for all standards, major speedup of identification for eia-j standard x faster carrier mute x j17 deemphasis x msp 34xxg version history all msp 34xxg data sheets no. 2/ 6251-525-2pds oct. 11, 2000 msp 34xxg

▲Up To Search▲

Price & Availability of MSP4458

	To Download MSP4458 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .